From: Andrew Cooper <andrew.cooper3@citrix.com>
Date: Sun, 5 Jun 2016 11:22:57 +0000 (+0100)
Subject: More pagetable order and entries information
X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=fc81e2030db6eca2243671b780f36fb97b21a894;p=people%2Fliuw%2Fxtf.git

More pagetable order and entries information

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
---

diff --git a/include/arch/x86/page-pae.h b/include/arch/x86/page-pae.h
index 76543d4..a0751ed 100644
--- a/include/arch/x86/page-pae.h
+++ b/include/arch/x86/page-pae.h
@@ -9,6 +9,9 @@
 /** PAE pagetable entries are 64 bits wide. */
 #define PAE_PTE_SZ 8
 
+/** PAE pagetables encode 9 bits of index. */
+#define PAE_PT_ORDER     9
+
 /** @{ */
 /** All PAE pagetables contain 512 entries. */
 #define PAE_L1_PT_ENTRIES (PAGE_SIZE / PAE_PTE_SZ)
diff --git a/include/arch/x86/page-pse.h b/include/arch/x86/page-pse.h
index a661ebb..c21fe96 100644
--- a/include/arch/x86/page-pse.h
+++ b/include/arch/x86/page-pse.h
@@ -9,6 +9,9 @@
 /** PSE pagetable entries are 32 bits wide. */
 #define PSE_PTE_SZ 4
 
+/** PAE pagetables encode 10 bits of index. */
+#define PSE_PT_ORDER 10
+
 /** @{ */
 /** All PSE pagetables contain 1024 entries. */
 #define PSE_L1_PT_ENTRIES (PAGE_SIZE / PSE_PTE_SZ)
diff --git a/include/arch/x86/page.h b/include/arch/x86/page.h
index d688b8d..e47dc7e 100644
--- a/include/arch/x86/page.h
+++ b/include/arch/x86/page.h
@@ -16,6 +16,7 @@
 
 #define PAGE_ORDER_4K           0
 #define PAGE_ORDER_2M           9
+#define PAGE_ORDER_4M           10
 #define PAGE_ORDER_1G           18
 
 #define _PAGE_PRESENT           0x0001
@@ -35,26 +36,40 @@
 
 #if CONFIG_PAGING_LEVELS == 2 /* PSE Paging */
 
+#define PT_ORDER PSE_PT_ORDER
+
 #define L1_PT_SHIFT PSE_L1_PT_SHIFT
 #define L2_PT_SHIFT PSE_L2_PT_SHIFT
 
+#define L1_PT_ENTRIES PSE_L1_PT_ENTRIES
+#define L2_PT_ENTRIES PSE_L2_PT_ENTRIES
+
 #else /* CONFIG_PAGING_LEVELS == 2 */ /* PAE Paging */
 
+#define PT_ORDER PAE_PT_ORDER
+
 #define L1_PT_SHIFT PAE_L1_PT_SHIFT
 #define L2_PT_SHIFT PAE_L2_PT_SHIFT
 
+#define L1_PT_ENTRIES PAE_L1_PT_ENTRIES
+#define L2_PT_ENTRIES PAE_L2_PT_ENTRIES
+
 #endif /* !CONFIG_PAGING_LEVELS == 2 */
 
 #if CONFIG_PAGING_LEVELS >= 3 /* PAE Paging */
 
 #define L3_PT_SHIFT PAE_L3_PT_SHIFT
 
+#define L3_PT_ENTRIES PAE_L3_PT_ENTRIES
+
 #endif /* CONFIG_PAGING_LEVELS >= 3 */
 
 #if CONFIG_PAGING_LEVELS >= 4 /* PAE Paging */
 
 #define L4_PT_SHIFT PAE_L4_PT_SHIFT
 
+#define L4_PT_ENTRIES PAE_L4_PT_ENTRIES
+
 #endif /* CONFIG_PAGING_LEVELS >= 4 */