From: Mark Langsdorf Date: Sat, 12 Nov 2011 16:15:19 +0000 (+0000) Subject: x86/amd: Eliminate cache flushing when entering C3 on select AMD processors X-Git-Tag: 4.0.4-rc1~33 X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=fbd80674b0ed69a3aca34b244dab1aa4e5897cf6;p=xen.git x86/amd: Eliminate cache flushing when entering C3 on select AMD processors AMD Fam15h processors have a shared cache. It does not need= to be be flushed when entering C3 and doing so causes reduces performance. Modify acpi_processor_power_init_bm_check to prevent these processors from flushing when entering C3. Signed-off-by: Mark Langsdorf xen-unstable changeset: 23511:450f1d198e1e xen-unstable date: Tue Jun 14 12:46:29 2011 +0100 Committed-by: Keir Fraser --- diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c index ce5cfa3b27..5fbbbcdd5f 100644 --- a/xen/arch/x86/acpi/cpu_idle.c +++ b/xen/arch/x86/acpi/cpu_idle.c @@ -549,7 +549,8 @@ static void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flag flags->bm_check = 0; if ( num_online_cpus() == 1 ) flags->bm_check = 1; - else if ( c->x86_vendor == X86_VENDOR_INTEL ) + else if ( (c->x86_vendor == X86_VENDOR_INTEL) || + ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 0x15)) ) { /* * Today all MP CPUs that support C3 share cache.