From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: Sat, 13 Feb 2021 14:09:18 +0000 (+0100)
Subject: target/mips/translate: Make gen_rdhwr() public
X-Git-Tag: qemu-xen-4.16.0-rc4~290^2~5
X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=f9fa53f19786c82cab2e7ca0274d6d9f9bb59f4f;p=qemu-xen.git

target/mips/translate: Make gen_rdhwr() public

We will use gen_rdhwr() outside of translate.c, make it public.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-28-f4bug@amsat.org>
---

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 256e2956c4..d4316c15d1 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -12349,7 +12349,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
     }
 }
 
-static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
+void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
 {
     TCGv t0;
 
diff --git a/target/mips/translate.h b/target/mips/translate.h
index e4f2f26de8..2b3c7a69ec 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -148,6 +148,8 @@ void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1);
 bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
 bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
 
+void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel);
+
 extern TCGv cpu_gpr[32], cpu_PC;
 #if defined(TARGET_MIPS64)
 extern TCGv_i64 cpu_gpr_hi[32];