From: Rob Herring <rob.herring@linaro.org>
Date: Tue, 18 Mar 2014 18:18:41 +0000 (-0500)
Subject: pl011: fix incorrect logic to set the RXFF flag
X-Git-Tag: qemu-xen-4.5.0-rc1~96^2~2
X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=f72dbf3d2629be75d50b4c98816c360d82e8a848;p=qemu-upstream-4.5-testing.git

pl011: fix incorrect logic to set the RXFF flag

The receive fifo full bit should be set when 1 character is received and
the fifo is disabled or when 16 characters are in the fifo.

Signed-off-by: Rob Herring <rob.herring@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1395166721-15716-4-git-send-email-robherring2@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---

diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index 11c3a75fc..644aad7cf 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -221,7 +221,7 @@ static void pl011_put_fifo(void *opaque, uint32_t value)
     s->read_fifo[slot] = value;
     s->read_count++;
     s->flags &= ~PL011_FLAG_RXFE;
-    if (s->cr & 0x10 || s->read_count == 16) {
+    if (!(s->lcr & 0x10) || s->read_count == 16) {
         s->flags |= PL011_FLAG_RXFF;
     }
     if (s->read_count == s->read_trigger) {