From: Jean-Philippe Brucker Date: Wed, 18 May 2016 16:32:19 +0000 (+0100) Subject: AArch64: get rid of EL2 trampoline X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=f01ed6c65ce267c37efc3d48fc68e36af2d00e62;p=people%2Fjulieng%2Fboot-wrapper-aarch64.git AArch64: get rid of EL2 trampoline There is no harm in initialising the platform from EL3, so we move the call into the boot_common path of CPU0, and take the opportunity to rename ns_init_system to init_platform. Caches and MMU are now disabled at EL3, and we can also move cache maintenance in the initial boot path of each CPU. This allows us to get rid of the EL2 layer, which makes AArch32 kernel support possible. Signed-off-by: Jean-Philippe Brucker Signed-off-by: Mark Rutland --- diff --git a/Makefile.am b/Makefile.am index 9189470..af0d7a6 100644 --- a/Makefile.am +++ b/Makefile.am @@ -92,7 +92,7 @@ CFLAGS += -Wall -fomit-frame-pointer CFLAGS += -ffunction-sections -fdata-sections LDFLAGS += --gc-sections -OFILES += boot_common.o bakery_lock.o ns.o $(GIC) cache.o lib.o +OFILES += boot_common.o bakery_lock.o platform.o $(GIC) cache.o lib.o OFILES += $(addprefix $(ARCH_SRC),boot.o stack.o $(BOOTMETHOD) utils.o) all: $(IMAGE) diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index 8bb536f..1602807 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -75,28 +75,18 @@ jump_kernel: ldr w0, flag_no_el3 cmp w0, #0 // Prepare Z flag - b.ne el2_trampoline // No EL3 - - mov x4, #SPSR_KERNEL - adr x5, el2_trampoline - msr elr_el3, x5 - msr spsr_el3, x4 - eret - -el2_trampoline: - bl flush_caches - - cpuid x0, x1 - b.ne 1f - bl ns_init_system - - /* Load kernel parameters */ -1: mov x0, x20 + mov x0, x20 mov x1, x21 mov x2, x22 mov x3, x23 - br x19 + b.eq 1f + br x19 // No EL3 + +1: mov x4, #SPSR_KERNEL + msr elr_el3, x19 + msr spsr_el3, x4 + eret .ltorg diff --git a/boot_common.c b/boot_common.c index 983c5d9..daf3198 100644 --- a/boot_common.c +++ b/boot_common.c @@ -12,6 +12,9 @@ extern unsigned long kernel; extern unsigned long dtb; +void init_platform(void); +void flush_caches(void); + void __noreturn jump_kernel(unsigned long address, unsigned long a0, unsigned long a1, @@ -55,7 +58,11 @@ void __noreturn spin(unsigned long *mbox, unsigned long invalid, int is_entry) void __noreturn first_spin(unsigned int cpu, unsigned long *mbox, unsigned long invalid) { + flush_caches(); + if (cpu == 0) { + init_platform(); + *mbox = (unsigned long)&kernel; sevl(); spin(mbox, invalid, 1); diff --git a/ns.c b/ns.c deleted file mode 100644 index 28f4376..0000000 --- a/ns.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * ns.c - code to initialise everything required when first booting. - * - * Copyright (C) 2015 ARM Limited. All rights reserved. - * - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE.txt file. - */ - -#include - -#include - -#define PL011_UARTDR 0x00 -#define PL011_UARTFR 0x18 -#define PL011_UARTIBRD 0x24 -#define PL011_UARTFBRD 0x28 -#define PL011_UART_LCR_H 0x2c -#define PL011_UARTCR 0x30 - -#define PL011_UARTFR_BUSY (1 << 3) -#define PL011_UARTFR_FIFO_FULL (1 << 5) - -#define PL011(reg) ((void *)UART_BASE + PL011_##reg) - -#define V2M_SYS_CFGDATA 0xa0 -#define V2M_SYS_CFGCTRL 0xa4 - -#define V2M_SYS(reg) ((void *)SYSREGS_BASE + V2M_SYS_##reg) - -static void print_string(const char *str) -{ - uint32_t flags; - - while (*str) { - do - flags = raw_readl(PL011(UARTFR)); - while (flags & PL011_UARTFR_FIFO_FULL); - - raw_writel(*str++, PL011(UARTDR)); - - do - flags = raw_readl(PL011(UARTFR)); - while (flags & PL011_UARTFR_BUSY); - } -} - -void ns_init_system(void) -{ - /* - * UART initialisation (38400 8N1) - */ - raw_writel(0x10, PL011(UARTIBRD)); - raw_writel(0x0, PL011(UARTFBRD)); - /* Set parameters to 8N1 and enable the FIFOs */ - raw_writel(0x70, PL011(UART_LCR_H)); - /* Enable the UART, TXen and RXen */ - raw_writel(0x301, PL011(UARTCR)); - - print_string("Boot-wrapper v0.1\r\n\r\n"); - - /* - * CLCD output site MB - */ - raw_writel(0x0, V2M_SYS(CFGDATA)); - /* START | WRITE | MUXFPGA | SITE_MB */ - raw_writel((1 << 31) | (1 << 30) | (7 << 20) | (0 << 16), - V2M_SYS(CFGCTRL)); -} diff --git a/platform.c b/platform.c new file mode 100644 index 0000000..16b15bc --- /dev/null +++ b/platform.c @@ -0,0 +1,69 @@ +/* + * platform.c - code to initialise everything required when first booting. + * + * Copyright (C) 2015 ARM Limited. All rights reserved. + * + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE.txt file. + */ + +#include + +#include + +#define PL011_UARTDR 0x00 +#define PL011_UARTFR 0x18 +#define PL011_UARTIBRD 0x24 +#define PL011_UARTFBRD 0x28 +#define PL011_UART_LCR_H 0x2c +#define PL011_UARTCR 0x30 + +#define PL011_UARTFR_BUSY (1 << 3) +#define PL011_UARTFR_FIFO_FULL (1 << 5) + +#define PL011(reg) ((void *)UART_BASE + PL011_##reg) + +#define V2M_SYS_CFGDATA 0xa0 +#define V2M_SYS_CFGCTRL 0xa4 + +#define V2M_SYS(reg) ((void *)SYSREGS_BASE + V2M_SYS_##reg) + +static void print_string(const char *str) +{ + uint32_t flags; + + while (*str) { + do + flags = raw_readl(PL011(UARTFR)); + while (flags & PL011_UARTFR_FIFO_FULL); + + raw_writel(*str++, PL011(UARTDR)); + + do + flags = raw_readl(PL011(UARTFR)); + while (flags & PL011_UARTFR_BUSY); + } +} + +void init_platform(void) +{ + /* + * UART initialisation (38400 8N1) + */ + raw_writel(0x10, PL011(UARTIBRD)); + raw_writel(0x0, PL011(UARTFBRD)); + /* Set parameters to 8N1 and enable the FIFOs */ + raw_writel(0x70, PL011(UART_LCR_H)); + /* Enable the UART, TXen and RXen */ + raw_writel(0x301, PL011(UARTCR)); + + print_string("Boot-wrapper v0.1\r\n\r\n"); + + /* + * CLCD output site MB + */ + raw_writel(0x0, V2M_SYS(CFGDATA)); + /* START | WRITE | MUXFPGA | SITE_MB */ + raw_writel((1 << 31) | (1 << 30) | (7 << 20) | (0 << 16), + V2M_SYS(CFGCTRL)); +}