From: Alistair Francis <alistair.francis@wdc.com>
Date: Fri, 27 Mar 2020 19:53:40 +0000 (-0700)
Subject: target/riscv: Set access as data_load when validating stage-2 PTEs
X-Git-Tag: qemu-xen-4.15.0~124^2~25
X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=efe9f9c820d1322729957a60ff785c9527a79ddf;p=qemu-xen.git

target/riscv: Set access as data_load when validating stage-2 PTEs

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 62fe1ecc8f..eda7057663 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -435,7 +435,7 @@ restart:
             hwaddr vbase;
 
             /* Do the second stage translation on the base PTE address. */
-            get_physical_address(env, &vbase, &vbase_prot, base, access_type,
+            get_physical_address(env, &vbase, &vbase_prot, base, MMU_DATA_LOAD,
                                  mmu_idx, false, true);
 
             pte_addr = vbase + idx * ptesize;