From: Kamala Narasimhan <kamala.narasimhan@citrix.com>
Date: Thu, 19 Mar 2009 19:17:22 +0000 (-0400)
Subject: Backport xen-unstable changeset - 19400 for 64/32 bit S3 resume issue.
X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=e82d5596caab01798ba72d59c6b93f557d243d31;p=xenclient%2Fxen.git

Backport xen-unstable changeset - 19400 for 64/32 bit S3 resume issue.

Also, remove previous stopgap patch to get around the same issue.
---

diff --git a/xen/arch/x86/acpi/suspend.c b/xen/arch/x86/acpi/suspend.c
index 3068590..edd94b2 100644
--- a/xen/arch/x86/acpi/suspend.c
+++ b/xen/arch/x86/acpi/suspend.c
@@ -31,13 +31,9 @@ void save_rest_processor_state(void)
 
 void restore_rest_processor_state(void)
 {
-    int cpu = smp_processor_id();
-    struct tss_struct *t = &init_tss[cpu];
     struct vcpu *v = current;
 
-    /* Rewriting the TSS desc is necessary to clear the Busy flag. */
-    set_tss_desc(cpu, t);
-    load_TR(cpu);
+    load_TR();
 
 #if defined(CONFIG_X86_64)
     /* Recover syscall MSRs */
diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index 42c6dc1..55d13fa 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -600,8 +600,7 @@ void __cpuinit cpu_init(void)
 	BUG_ON((get_stack_bottom() & 15) != 0);
 	t->rsp0 = get_stack_bottom();
 #endif
-	set_tss_desc(cpu,t);
-	load_TR(cpu);
+	load_TR();
 	asm volatile ( "lldt %%ax" : : "a" (0) );
 
 	/* Clear all 6 debug registers: */
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 3cc884b..2798fc7 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -2978,20 +2978,31 @@ void set_intr_gate(unsigned int n, void *addr)
     __set_intr_gate(n, 0, addr);
 }
 
-void set_tss_desc(unsigned int n, void *addr)
+void load_TR(void)
 {
+    struct tss_struct *tss = &init_tss[smp_processor_id()];
+    struct desc_ptr old_gdt, tss_gdt = {
+        .base = (long)(this_cpu(gdt_table) - FIRST_RESERVED_GDT_ENTRY),
+        .limit = LAST_RESERVED_GDT_BYTE
+    };
+
     _set_tssldt_desc(
-        per_cpu(gdt_table, n) + TSS_ENTRY - FIRST_RESERVED_GDT_ENTRY,
-        (unsigned long)addr,
+        this_cpu(gdt_table) + TSS_ENTRY - FIRST_RESERVED_GDT_ENTRY,
+        (unsigned long)tss,
         offsetof(struct tss_struct, __cacheline_filler) - 1,
         9);
 #ifdef CONFIG_COMPAT
     _set_tssldt_desc(
-        per_cpu(compat_gdt_table, n) + TSS_ENTRY - FIRST_RESERVED_GDT_ENTRY,
-        (unsigned long)addr,
+        this_cpu(compat_gdt_table) + TSS_ENTRY - FIRST_RESERVED_GDT_ENTRY,
+        (unsigned long)tss,
         offsetof(struct tss_struct, __cacheline_filler) - 1,
-        9);
+        11);
 #endif
+
+    /* Switch to non-compat GDT (which has B bit clear) to execute LTR. */
+    asm volatile (
+        "sgdt %1; lgdt %2; ltr %%ax; lgdt %1"
+        : : "a" (TSS_ENTRY << 3), "m" (old_gdt), "m" (tss_gdt) : "memory" );
 }
 
 void __devinit percpu_traps_init(void)
diff --git a/xen/include/asm-x86/desc.h b/xen/include/asm-x86/desc.h
index f59f372..20eb8db 100644
--- a/xen/include/asm-x86/desc.h
+++ b/xen/include/asm-x86/desc.h
@@ -57,8 +57,6 @@
 
 #ifndef __ASSEMBLY__
 
-#define load_TR(n)  __asm__ __volatile__ ("ltr  %%ax" : : "a" (TSS_ENTRY<<3) )
-
 #if defined(__x86_64__)
 #define GUEST_KERNEL_RPL(d) (is_pv_32bit_domain(d) ? 1 : 3)
 #elif defined(__i386__)
@@ -219,7 +217,7 @@ DECLARE_PER_CPU(struct desc_struct *, compat_gdt_table);
 #endif
 
 extern void set_intr_gate(unsigned int irq, void * addr);
-extern void set_tss_desc(unsigned int n, void *addr);
+extern void load_TR(void);
 
 #endif /* !__ASSEMBLY__ */