From: Kevin O'Connor <kevin@koconnor.net>
Date: Tue, 10 Nov 2009 00:30:17 +0000 (-0500)
Subject: Properly mask value for MTRR mask.
X-Git-Tag: rel-0.5.0~38
X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=e622ff635f8b1b53cbb433764f6f42e21350df6a;p=seabios.git

Properly mask value for MTRR mask.

Signed-off-by: Magnus Christensson <mch@virtutech.com>
---

diff --git a/src/mtrr.c b/src/mtrr.c
index a9cd5f7..6bd0dba 100644
--- a/src/mtrr.c
+++ b/src/mtrr.c
@@ -29,7 +29,7 @@ void mtrr_setup(void)
     if (CONFIG_COREBOOT)
         return;
 
-    u32 eax, ebx, ecx, cpuid_features;
+    u32 eax, ebx, ecx, edx, cpuid_features;
     cpuid(1, &eax, &ebx, &ecx, &cpuid_features);
     if (!(cpuid_features & CPUID_MTRR))
         return;
@@ -73,6 +73,16 @@ void mtrr_setup(void)
     wrmsr_smp(MSR_MTRRfix4K_F8000, 0);
     /* Mark 3.5-4GB as UC, anything not specified defaults to WB */
     wrmsr_smp(MTRRphysBase_MSR(0), 0xe0000000ull | 0);
-    wrmsr_smp(MTRRphysMask_MSR(0), ~(0x20000000ull - 1) | 0x800);
+
+    int phys_bits = 36;
+    cpuid(0x80000000u, &eax, &ebx, &ecx, &edx);
+    if (eax >= 0x80000008) {
+            /* Get physical bits from leaf 0x80000008 (if available) */
+            cpuid(0x80000008u, &eax, &ebx, &ecx, &edx);
+            phys_bits = eax & 0xff;
+    }
+    u64 phys_mask = ((1ull << phys_bits) - 1);
+    wrmsr_smp(MTRRphysMask_MSR(0), (~(0x20000000ull - 1) & phys_mask) | 0x800);
+
     wrmsr_smp(MSR_MTRRdefType, 0xc06);
 }