From: Peter Crosthwaite Date: Wed, 4 Dec 2013 06:00:54 +0000 (-0800) Subject: net/cadence_gem: Fix register w1c logic X-Git-Tag: qemu-xen-4.5.0-rc1~294^2~10 X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=e2314fda62c42c89f91dcf104ed3702170a90308;p=qemu-upstream-4.5-testing.git net/cadence_gem: Fix register w1c logic This write-1-clear logic was incorrect. It was always clearing w1c bits regardless of whether the written value was 1 or not. i.e. it was implementing a write-anything-to-clear strategy. Signed-off-by: Peter Crosthwaite Reviewed-by: Peter Maydell Message-id: ed905b04d3343966ded425f06aa2224bc7a35b59.1386136219.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell --- diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 1619507e5..f2c734ef2 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -1112,15 +1112,14 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val, /* Squash bits which are read only in write value */ val &= ~(s->regs_ro[offset]); - /* Preserve (only) bits which are read only in register */ - readonly = s->regs[offset]; - readonly &= s->regs_ro[offset]; - - /* Squash bits which are write 1 to clear */ - val &= ~(s->regs_w1c[offset] & val); + /* Preserve (only) bits which are read only and wtc in register */ + readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]); /* Copy register write to backing store */ - s->regs[offset] = val | readonly; + s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly; + + /* do w1c */ + s->regs[offset] &= ~(s->regs_w1c[offset] & val); /* Handle register write side effects */ switch (offset) {