From: Rahul Pathak Date: Tue, 16 Aug 2022 04:54:08 +0000 (+0530) Subject: target/riscv: Add xicondops in ISA entry X-Git-Tag: qemu-xen-4.18.0-rc5~536^2~9 X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=e0dea2f55f678a1aa1dab3a25c13f52d68b4ec2b;p=qemu-xen.git target/riscv: Add xicondops in ISA entry XVentanaCondOps is Ventana custom extension. Add its extension entry in the ISA Ext array Signed-off-by: Rahul Pathak Reviewed-by: Alistair Francis Message-id: 20220816045408.1231135-1-rpathak@ventanamicro.com Signed-off-by: Alistair Francis --- diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d4635c7df4..e0d5941230 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -102,6 +102,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), + ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), }; static bool isa_ext_is_enabled(RISCVCPU *cpu,