From: Roger Pau Monné <roger.pau@citrix.com>
Date: Mon, 16 Jul 2018 13:10:49 +0000 (+0200)
Subject: hvm/mtrr: copy hardware state for Dom0
X-Git-Tag: 4.12.0-rc1~969
X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=d8b0840bb90711e93b6994e50c728bbbf0f012a0;p=xen.git

hvm/mtrr: copy hardware state for Dom0

Copy the state found on the hardware when creating a PVH Dom0. Since
the memory map provided to a PVH Dom0 is based on the native one using
the same set of MTRR ranges should provide Dom0 with a sane MTRR state
without having to manually build it in Xen.

Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
---

diff --git a/xen/arch/x86/hvm/mtrr.c b/xen/arch/x86/hvm/mtrr.c
index 4021d972fe..2b00993a7b 100644
--- a/xen/arch/x86/hvm/mtrr.c
+++ b/xen/arch/x86/hvm/mtrr.c
@@ -185,6 +185,32 @@ int hvm_vcpu_cacheattr_init(struct vcpu *v)
         ((uint64_t)PAT_TYPE_UC_MINUS << 48) |       /* PAT6: UC- */
         ((uint64_t)PAT_TYPE_UNCACHABLE << 56);      /* PAT7: UC */
 
+    if ( is_hardware_domain(v->domain) )
+    {
+        /* Copy values from the host. */
+        struct domain *d = v->domain;
+        unsigned int i;
+
+        if ( mtrr_state.have_fixed )
+            for ( i = 0; i < NUM_FIXED_MSR; i++ )
+                mtrr_fix_range_msr_set(d, m, i,
+                                      ((uint64_t *)mtrr_state.fixed_ranges)[i]);
+
+        for ( i = 0; i < num_var_ranges; i++ )
+        {
+            mtrr_var_range_msr_set(d, m, MSR_IA32_MTRR_PHYSBASE(i),
+                                   mtrr_state.var_ranges[i].base);
+            mtrr_var_range_msr_set(d, m, MSR_IA32_MTRR_PHYSMASK(i),
+                                   mtrr_state.var_ranges[i].mask);
+        }
+
+        mtrr_def_type_msr_set(d, m,
+                              mtrr_state.def_type |
+                              MASK_INSR(mtrr_state.fixed_enabled,
+                                        MTRRdefType_FE) |
+                              MASK_INSR(mtrr_state.enabled, MTRRdefType_E));
+    }
+
     return 0;
 }