From: Richard Sandiford Date: Sat, 26 Nov 2011 03:37:07 +0000 (+0000) Subject: mips: Fix BC1ANY[24]F instructions X-Git-Tag: v1.1.0-rc3~12 X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=d7f66b52dee3dd7423a28c0ceb600aec388859cb;p=qemu-xen-unstable.git mips: Fix BC1ANY[24]F instructions There's some dodgy application of De Morgan's law in the emulation of the MIPS BC1ANY[24]F instructions: they end up branching only if all CCs are false, rather than if one CC is. Tested on mips64-linux-gnu, where it fixes the GCC MIPS3D tests. Signed-off-by: Richard Sandiford Reviewed-by: Richard Henderson Signed-off-by: Blue Swirl --- diff --git a/target-mips/translate.c b/target-mips/translate.c index f5297b0392..0c563eedfa 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -6099,7 +6099,7 @@ static void gen_compute_branch1 (CPUMIPSState *env, DisasContext *ctx, uint32_t TCGv_i32 t1 = tcg_temp_new_i32(); tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); - tcg_gen_nor_i32(t0, t0, t1); + tcg_gen_nand_i32(t0, t0, t1); tcg_temp_free_i32(t1); tcg_gen_andi_i32(t0, t0, 1); tcg_gen_extu_i32_tl(bcond, t0); @@ -6123,11 +6123,11 @@ static void gen_compute_branch1 (CPUMIPSState *env, DisasContext *ctx, uint32_t TCGv_i32 t1 = tcg_temp_new_i32(); tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); - tcg_gen_or_i32(t0, t0, t1); + tcg_gen_and_i32(t0, t0, t1); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+2)); - tcg_gen_or_i32(t0, t0, t1); + tcg_gen_and_i32(t0, t0, t1); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+3)); - tcg_gen_nor_i32(t0, t0, t1); + tcg_gen_nand_i32(t0, t0, t1); tcg_temp_free_i32(t1); tcg_gen_andi_i32(t0, t0, 1); tcg_gen_extu_i32_tl(bcond, t0);