From: Richard Henderson Date: Mon, 14 Sep 2015 13:39:48 +0000 (+0100) Subject: target-arm: Eliminate unnecessary zero-extend in disas_bitfield X-Git-Tag: qemu-xen-4.8.0-rc1~817^2~13 X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=d3a77b42decd0cbfa62a5526e67d1d6d380c83a9;p=qemu-xen.git target-arm: Eliminate unnecessary zero-extend in disas_bitfield For !SF, this initial ext32u can't be optimized away by the current TCG code generator. (It would require backward bit liveness propagation.) But since the range of bits for !SF are already constrained by unallocated_encoding, we'll never reference the high bits anyway. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 1441909103-24666-10-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell --- diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index f2f8443483..3ab0b42258 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -3015,7 +3015,11 @@ static void disas_bitfield(DisasContext *s, uint32_t insn) } tcg_rd = cpu_reg(s, rd); - tcg_tmp = read_cpu_reg(s, rn, sf); + + /* Suppress the zero-extend for !sf. Since RI and SI are constrained + to be smaller than bitsize, we'll never reference data outside the + low 32-bits anyway. */ + tcg_tmp = read_cpu_reg(s, rn, 1); /* Recognize the common aliases. */ if (opc == 0) { /* SBFM */