From: Tony Luck <tony.luck@intel.com>
Date: Mon, 2 Mar 2020 14:40:09 +0000 (+0100)
Subject: x86/mce: add Xeon Icelake to list of CPUs that support PPIN
X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=cb4684e34602810c93c1e88adfd51d0e17177a99;p=people%2Fdwmw2%2Fxen.git

x86/mce: add Xeon Icelake to list of CPUs that support PPIN

New CPU model, same MSRs to control and read the inventory number.

Signed-off-by: Tony Luck <tony.luck@intel.com>
[Linux commit dc6b025de95bcd22ff37c4fabb022ec8a027abf1]
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
---

diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/mce_intel.c
index 6f23ea5329..29b9983172 100644
--- a/xen/arch/x86/cpu/mcheck/mce_intel.c
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c
@@ -871,6 +871,7 @@ static void intel_init_ppin(const struct cpuinfo_x86 *c)
     case 0x55: /* Skylake X */
     case 0x56: /* Broadwell Xeon D */
     case 0x57: /* Knights Landing */
+    case 0x6a: /* Icelake X */
     case 0x85: /* Knights Mill */
 
         if ( (c != &boot_cpu_data && !ppin_msr) ||