From: Peter Maydell <peter.maydell@linaro.org>
Date: Thu, 19 Nov 2020 21:56:07 +0000 (+0000)
Subject: target/arm: Implement v8.1M REVIDR register
X-Git-Tag: qemu-xen-4.16.0-rc4~444^2~8
X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=cb45adb654bb34de9de6301b6981972dd107e342;p=qemu-xen.git

target/arm: Implement v8.1M REVIDR register

In v8.1M a REVIDR register is defined, which is at address 0xe00ecfc
and is a read-only IMPDEF register providing implementation specific
minor revision information, like the v8A REVIDR_EL1. Implement this.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-19-peter.maydell@linaro.org
---

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index be3bc1f1f4..effc4a784c 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -1025,6 +1025,11 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
         }
         return val;
     }
+    case 0xcfc:
+        if (!arm_feature(&cpu->env, ARM_FEATURE_V8_1M)) {
+            goto bad_offset;
+        }
+        return cpu->revidr;
     case 0xd00: /* CPUID Base.  */
         return cpu->midr;
     case 0xd04: /* Interrupt Control State (ICSR) */