From: Jan Beulich <jbeulich@suse.com>
Date: Thu, 27 Mar 2025 14:05:11 +0000 (+0100)
Subject: x86/PVH: expose OEMx ACPI tables to Dom0
X-Git-Tag: RELEASE-4.19.2~23
X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=c9f077bc4107728a41b88acdbcee90dad9901aa6;p=xen.git

x86/PVH: expose OEMx ACPI tables to Dom0

What they contain we don't know, but we can't sensibly hide them. On my
Skylake system OEM1 (with a description of "INTEL  CPU EIST") is what
contains all the _PCT, _PPC, and _PSS methods, i.e. about everything
needed for cpufreq. (_PSD interestingly are in an SSDT there.)

Further OEM2 there has a description of "INTEL  CPU  HWP", while OEM4
has "INTEL  CPU  CST". Pretty clearly all three need exposing for
cpufreq and cpuidle to work.

Fixes: 8b1a5268daf0 ("pvh/dom0: whitelist PVH Dom0 ACPI tables")
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
master commit: 6378909b41c40187a79df1d38ca4791b34393d67
master date: 2025-03-26 12:32:03 +0100
---

diff --git a/xen/arch/x86/hvm/dom0_build.c b/xen/arch/x86/hvm/dom0_build.c
index 716879b710..4a094ae317 100644
--- a/xen/arch/x86/hvm/dom0_build.c
+++ b/xen/arch/x86/hvm/dom0_build.c
@@ -1010,12 +1010,20 @@ static bool __init pvh_acpi_table_allowed(const char *sig,
             return true;
         else
         {
+    skip:
             printk("Skipping table %.4s in non-ACPI non-reserved region\n",
                    sig);
             return false;
         }
     }
 
+    if ( !strncmp(sig, "OEM", 3) )
+    {
+        if ( acpi_memory_banned(address, size) )
+            goto skip;
+        return true;
+    }
+
     return false;
 }