From: Andrew Cooper Date: Fri, 22 May 2020 14:46:44 +0000 (+0100) Subject: x86/idle: Extend ISR/C6 erratum workaround to Haswell X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=b72d8870b5f68f06b083e6bfdb28f081bcb6ab3b;p=people%2Fdariof%2Fxen.git x86/idle: Extend ISR/C6 erratum workaround to Haswell This bug was first discovered against Haswell. It is definitely affected. (The XenServer ticket for this bug was opened on 2013-05-30 which is coming up on 7 years old, and predates Broadwell). Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c index 178cb607c2..a2248ea11f 100644 --- a/xen/arch/x86/acpi/cpu_idle.c +++ b/xen/arch/x86/acpi/cpu_idle.c @@ -583,8 +583,16 @@ bool errata_c6_workaround(void) * registers), the processor may dispatch the second interrupt (from * the IRR bit) before the first interrupt has completed and written to * the EOI register, causing the first interrupt to never complete. + * + * Note: Haswell hasn't had errata issued, but this issue was first + * discovered on Haswell hardware, and is affected. */ static const struct x86_cpu_id isr_errata[] = { + /* Haswell */ + INTEL_FAM6_MODEL(0x3c), + INTEL_FAM6_MODEL(0x3f), + INTEL_FAM6_MODEL(0x45), + INTEL_FAM6_MODEL(0x46), /* Broadwell */ INTEL_FAM6_MODEL(0x47), INTEL_FAM6_MODEL(0x3d),