From: Peter Maydell <peter.maydell@linaro.org>
Date: Wed, 9 Nov 2011 20:46:35 +0000 (+0000)
Subject: hw/pxa2xx.c: Fix handling of R/WC bits in PMCR
X-Git-Tag: qemu-xen-4.3.0-rc1~2011
X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=afd4a6522;p=qemu-upstream-4.5-testing.git

hw/pxa2xx.c: Fix handling of R/WC bits in PMCR

Fix a bug in handling the write-one-to-clear bits in the PMCR
which meant that we would always clear the bit even if the
value written was a zero. Spotted by Coverity (see bug 887883).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
---

diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c
index bfc28a999..d38b92292 100644
--- a/hw/pxa2xx.c
+++ b/hw/pxa2xx.c
@@ -114,7 +114,9 @@ static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
 
     switch (addr) {
     case PMCR:
-        s->pm_regs[addr >> 2] &= 0x15 & ~(value & 0x2a);
+        /* Clear the write-one-to-clear bits... */
+        s->pm_regs[addr >> 2] &= ~(value & 0x2a);
+        /* ...and set the plain r/w bits */
         s->pm_regs[addr >> 2] |= value & 0x15;
         break;