From: Michalis Pappas <mpp@opensynergy.com>
Date: Thu, 12 Sep 2019 08:35:31 +0000 (+0200)
Subject: plat/common: Fix cache policy MAIR definitions
X-Git-Tag: RELEASE-0.6~146
X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=afb301e8f66efc95b2e68b108bf86ae7cb4aeb54;p=unikraft%2Funikraft.git

plat/common: Fix cache policy MAIR definitions

Fix transposed cache attributes in MAIR_ATTR for ARM64

Signed-off-by: Michalis Pappas <Michalis.Pappas@opensynergy.com>
Acked-by: Renê de Souza Pinto <Rene.deSouzaPinto@opensynergy.com>
Reviewed-by: Răzvan Vîrtan <virtanrazvan@gmail.com>
Tested-by: Unikraft CI <monkey@unikraft.io>
GitHub-Pull-Request: #170
---

diff --git a/plat/common/include/arm/arm64/cpu_defs.h b/plat/common/include/arm/arm64/cpu_defs.h
index 53be825eb..7d87f7c0b 100644
--- a/plat/common/include/arm/arm64/cpu_defs.h
+++ b/plat/common/include/arm/arm64/cpu_defs.h
@@ -89,8 +89,8 @@
 		MAIR_ATTR(MAIR_DEVICE_nGnRE, DEVICE_nGnRE) |   \
 		MAIR_ATTR(MAIR_DEVICE_GRE, DEVICE_GRE) |       \
 		MAIR_ATTR(MAIR_NORMAL_NC, NORMAL_NC) |         \
-		MAIR_ATTR(MAIR_NORMAL_WB, NORMAL_WT) |         \
-		MAIR_ATTR(MAIR_NORMAL_WT, NORMAL_WB))
+		MAIR_ATTR(MAIR_NORMAL_WT, NORMAL_WT) |         \
+		MAIR_ATTR(MAIR_NORMAL_WB, NORMAL_WB))
 
 /* TCR_EL1 - Translation Control Register */
 #define TCR_ASID_16	(1 << 36)