From: Richard Henderson <rth@twiddle.net>
Date: Wed, 5 Mar 2014 20:27:23 +0000 (-0800)
Subject: tcg-sparc: Support trunc_shr_i32
X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=a24fba935af42107f24212f8adbe44ec2b9bd09d;p=osstest%2Fqemu.git

tcg-sparc: Support trunc_shr_i32

Unlike a 64-bit shift op, allows the output to be in %l or %i registers
for sparcv8plus.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---

diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index f1226ab9e..4287bbefa 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -1482,6 +1482,13 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
     case INDEX_op_ext32u_i64:
         tcg_out_arithi(s, args[0], args[1], 0, SHIFT_SRL);
         break;
+    case INDEX_op_trunc_shr_i32:
+        if (args[2] == 0) {
+            tcg_out_mov(s, TCG_TYPE_I32, args[0], args[1]);
+        } else {
+            tcg_out_arithi(s, args[0], args[1], args[2], SHIFT_SRLX);
+        }
+        break;
 
     case INDEX_op_brcond_i64:
         tcg_out_brcond_i64(s, args[2], args[0], args[1], const_args[1],
@@ -1593,6 +1600,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
 
     { INDEX_op_ext32s_i64, { "r", "r" } },
     { INDEX_op_ext32u_i64, { "r", "r" } },
+    { INDEX_op_trunc_shr_i32,  { "r", "r" } },
 
     { INDEX_op_brcond_i64, { "rZ", "rJ" } },
     { INDEX_op_setcond_i64, { "r", "rZ", "rJ" } },
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index f44739fd0..61fd6b8da 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -117,7 +117,7 @@ typedef enum {
 #define TCG_TARGET_HAS_mulsh_i32        0
 
 #if TCG_TARGET_REG_BITS == 64
-#define TCG_TARGET_HAS_trunc_shr_i32    0
+#define TCG_TARGET_HAS_trunc_shr_i32    1
 #define TCG_TARGET_HAS_div_i64          1
 #define TCG_TARGET_HAS_rem_i64          0
 #define TCG_TARGET_HAS_rot_i64          0