From: aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Tue, 22 Apr 2008 21:57:57 +0000 (+0000)
Subject: Fix PHYS_ADDR_MASK: upper bits of a PTE are reserved so they are 52 bits
X-Git-Tag: xen-3.3.0-rc1~194^2^2~210
X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=a23a663b6555497b1569e407cc8edff09787decb;p=qemu-xen-4.1-testing.git

Fix PHYS_ADDR_MASK: upper bits of a PTE are reserved so they are 52 bits
long. Thanks to Paul Brook for noticing that.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4242 c046a42c-6fe2-441c-8c8c-71466251a162
---

diff --git a/target-i386/helper2.c b/target-i386/helper2.c
index d5dc96ba1..106720aa7 100644
--- a/target-i386/helper2.c
+++ b/target-i386/helper2.c
@@ -800,7 +800,8 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
 
 #else
 
-#define PHYS_ADDR_MASK (~0xfff)
+/* Bits 52-62 of a PTE are reserved. Bit 63 is the NX bit. */
+#define PHYS_ADDR_MASK 0xffffffffff000L
 
 /* return value:
    -1 = cannot handle fault