From: Jan Beulich Date: Tue, 5 Sep 2017 15:31:01 +0000 (+0200) Subject: x86emul: correct VEX.W handling for non-64-bit VPINSRD X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=9c2babd05a213f8802e3cc1c64a2af932b5cbd7d;p=people%2Froyger%2Fxen.git x86emul: correct VEX.W handling for non-64-bit VPINSRD Going though the XED commits from the last couple of months made me notice that VPINSRD, other than VPEXTRD, does not clear VEX.W for non- 64-bit modes, leading to an insertion of stray 32-bits of zero in case the original instruction had the bit set. Also remove a pointless fall-through in VPEXTRW handling, bringing things in line with VPINSRW. Signed-off-by: Jan Beulich Reviewed-by: Andrew Cooper --- diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emulate/x86_emulate.c index 85e36f873e..0d76351163 100644 --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -6741,10 +6741,9 @@ x86_emulate( ea.type = OP_MEM; goto simd_0f_int_imm8; + CASE_SIMD_PACKED_INT(0x0f, 0xc5): /* pextrw $imm8,{,x}mm,reg */ case X86EMUL_OPC_VEX_66(0x0f, 0xc5): /* vpextrw $imm8,xmm,reg */ generate_exception_if(vex.l, EXC_UD); - /* fall through */ - CASE_SIMD_PACKED_INT(0x0f, 0xc5): /* pextrw $imm8,{,x}mm,reg */ opc = init_prefixes(stub); opc[0] = b; /* Convert GPR destination to %rAX. */ @@ -7523,6 +7522,8 @@ x86_emulate( case X86EMUL_OPC_VEX_66(0x0f3a, 0x20): /* vpinsrb $imm8,r32/m8,xmm,xmm */ case X86EMUL_OPC_VEX_66(0x0f3a, 0x22): /* vpinsr{d,q} $imm8,r/m,xmm,xmm */ generate_exception_if(vex.l, EXC_UD); + if ( !mode_64bit() ) + vex.w = 0; memcpy(mmvalp, &src.val, op_bytes); ea.type = OP_MEM; op_bytes = src.bytes;