From: Fredrik Noring <noring@nocrew.org>
Date: Wed, 7 Nov 2018 19:19:45 +0000 (+0100)
Subject: target/mips: Guard check_insn with INSN_R5900 check
X-Git-Tag: qemu-xen-4.13.0-rc1~539^2~5
X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=992e8176d36882983bb04f0259f7151a36d003a1;p=qemu-xen.git

target/mips: Guard check_insn with INSN_R5900 check

Explicitely mark handling of PREF instruction for R5900 as
treating the same as NOP.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---

diff --git a/target/mips/translate.c b/target/mips/translate.c
index c79da3c2e4..714f2e6be4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28357,9 +28357,12 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
         break;
     case OPC_PREF:
         check_insn_opc_removed(ctx, ISA_MIPS32R6);
-        check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 |
-                   INSN_R5900);
-        /* Treat as NOP. */
+        if (ctx->insn_flags & INSN_R5900) {
+            /* Treat as NOP. */
+        } else {
+            check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
+            /* Treat as NOP. */
+        }
         break;
 
     /* Floating point (COP1). */