From: Ian Campbell Date: Fri, 13 Jun 2014 12:15:04 +0000 (+0100) Subject: xen: arm: Implement OSDLR_EL1 trap as RAZ/WO. X-Git-Tag: 4.5.0-rc1~634 X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=92b0b80f0d2d29d0e80bf35ea839ed6058b7f0fa;p=xen.git xen: arm: Implement OSDLR_EL1 trap as RAZ/WO. I'm not sure why this wasn't added at the same time as the other debug registers. Signed-off-by: Ian Campbell Acked-by: Julien Grall --- diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 9bc3198398..994b654846 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -1596,9 +1596,11 @@ static void do_sysreg(struct cpu_user_regs *regs, /* - Breakpoints */ HSR_SYSREG_DBG_CASES(DBGBVR): HSR_SYSREG_DBG_CASES(DBGBCR): - /* - Watchpoints */ + /* - Watchpoints */ HSR_SYSREG_DBG_CASES(DBGWVR): HSR_SYSREG_DBG_CASES(DBGWCR): + /* - Double Lock Register */ + case HSR_SYSREG_OSDLR_EL1: if ( hsr.sysreg.read ) *x = 0; /* else: write ignored */ diff --git a/xen/include/asm-arm/sysregs.h b/xen/include/asm-arm/sysregs.h index 4a4de342b3..b00871c18f 100644 --- a/xen/include/asm-arm/sysregs.h +++ b/xen/include/asm-arm/sysregs.h @@ -42,6 +42,7 @@ #define HSR_SYSREG_MDSCR_EL1 HSR_SYSREG(2,0,c0,c2,2) #define HSR_SYSREG_OSLAR_EL1 HSR_SYSREG(2,0,c1,c0,4) +#define HSR_SYSREG_OSDLR_EL1 HSR_SYSREG(2,0,c1,c3,4) #define HSR_SYSREG_DBGBVRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,4) #define HSR_SYSREG_DBGBCRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,5)