From: Philipp Tomsich Date: Thu, 3 Feb 2022 15:39:45 +0000 (+0100) Subject: target/riscv: fix inverted checks for ext_zb[abcs] X-Git-Tag: qemu-xen-4.17.0-rc4~76^2~12 X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=90f9e35b7895b32a451df82c773d95faba910f49;p=qemu-xen.git target/riscv: fix inverted checks for ext_zb[abcs] While changing to the use of cfg_ptr, the conditions for REQUIRE_ZB[ABCS] inadvertently became inverted and slipped through the initial testing (which used RV64GC_XVentanaCondOps as a target). This fixes the regression. Tested against SPEC2017 w/ GCC 12 (prerelease) for RV64GC_zba_zbb_zbc_zbs. Fixes: f2a32bec8f0da99 ("target/riscv: access cfg structure through DisasContext") Signed-off-by: Philipp Tomsich Reviewed-by: Alistair Francis Message-Id: <20220203153946.2676353-1-philipp.tomsich@vrull.eu> Signed-off-by: Alistair Francis --- diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index f9bd3b7ec4..e8519a6d69 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -19,25 +19,25 @@ */ #define REQUIRE_ZBA(ctx) do { \ - if (ctx->cfg_ptr->ext_zba) { \ + if (!ctx->cfg_ptr->ext_zba) { \ return false; \ } \ } while (0) #define REQUIRE_ZBB(ctx) do { \ - if (ctx->cfg_ptr->ext_zbb) { \ + if (!ctx->cfg_ptr->ext_zbb) { \ return false; \ } \ } while (0) #define REQUIRE_ZBC(ctx) do { \ - if (ctx->cfg_ptr->ext_zbc) { \ + if (!ctx->cfg_ptr->ext_zbc) { \ return false; \ } \ } while (0) #define REQUIRE_ZBS(ctx) do { \ - if (ctx->cfg_ptr->ext_zbs) { \ + if (!ctx->cfg_ptr->ext_zbs) { \ return false; \ } \ } while (0)