From: Jan Beulich <jbeulich@suse.com>
Date: Fri, 5 Feb 2021 07:52:54 +0000 (+0100)
Subject: x86/msr: fix handling of MSR_IA32_PERF_{STATUS/CTL} (again, part 2)
X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=8d26cdd3b66ab86d560dacd763d76ff3da95723e;p=xen.git

x86/msr: fix handling of MSR_IA32_PERF_{STATUS/CTL} (again, part 2)

X86_VENDOR_* aren't bit masks in the older trees.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
---

diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c
index aefe0cbb4b..f53a186f6c 100644
--- a/xen/arch/x86/msr.c
+++ b/xen/arch/x86/msr.c
@@ -441,7 +441,8 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val)
          * a cpufreq controller dom0 which has full access.
          */
     case MSR_IA32_PERF_CTL:
-        if ( !(cp->x86_vendor & (X86_VENDOR_INTEL | X86_VENDOR_CENTAUR)) )
+        if ( cp->x86_vendor != X86_VENDOR_INTEL &&
+             cp->x86_vendor != X86_VENDOR_CENTAUR )
             goto gp_fault;
 
         if ( likely(!is_cpufreq_controller(d)) || wrmsr_safe(msr, val) == 0 )