From: Andrew Cooper <andrew.cooper3@citrix.com>
Date: Fri, 29 Sep 2023 17:44:31 +0000 (+0100)
Subject: debug-regs: Check MSR_DR_ADDR_MASK state too
X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=846e8255e41ff68c59fa3d52aa7f2a3fdfc58633;p=people%2Fandrewcoop%2Fxen-test-framework.git

debug-regs: Check MSR_DR_ADDR_MASK state too

Broken currently as PV regressed MSR_DEBUGCTL.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
---

diff --git a/arch/x86/include/arch/cpuid.h b/arch/x86/include/arch/cpuid.h
index 4a117a9..e6d6a8c 100644
--- a/arch/x86/include/arch/cpuid.h
+++ b/arch/x86/include/arch/cpuid.h
@@ -87,6 +87,7 @@ static inline bool cpu_has(unsigned int feature)
 #define cpu_has_lm              cpu_has(X86_FEATURE_LM)
 
 #define cpu_has_svm             cpu_has(X86_FEATURE_SVM)
+#define cpu_has_dbext           cpu_has(X86_FEATURE_DBEXT)
 
 #define cpu_has_fsgsbase        cpu_has(X86_FEATURE_FSGSBASE)
 #define cpu_has_hle             cpu_has(X86_FEATURE_HLE)
diff --git a/arch/x86/include/arch/msr-index.h b/arch/x86/include/arch/msr-index.h
index 4b7f8e5..be7ba0d 100644
--- a/arch/x86/include/arch/msr-index.h
+++ b/arch/x86/include/arch/msr-index.h
@@ -65,6 +65,11 @@
 #define MSR_GS_BASE                     0xc0000101
 #define MSR_SHADOW_GS_BASE              0xc0000102
 
+#define MSR_DR0_ADDR_MASK               0xc0011027
+#define MSR_DR1_ADDR_MASK               0xc0011019
+#define MSR_DR2_ADDR_MASK               0xc001101a
+#define MSR_DR3_ADDR_MASK               0xc001101b
+
 #endif /* XTF_X86_MSR_INDEX_H */
 
 /*
diff --git a/tests/debug-regs/main.c b/tests/debug-regs/main.c
index 19c8889..5e5cd84 100644
--- a/tests/debug-regs/main.c
+++ b/tests/debug-regs/main.c
@@ -43,14 +43,20 @@
 
 const char test_title[] = "Debugging facility tests";
 
-static void check_initial_state(unsigned int dr, unsigned long exp,
-                                unsigned long got)
+static void check_init_dr(unsigned int dr, unsigned long exp, unsigned long got)
 {
     if ( got != exp )
         xtf_failure("  Fail: %%dr%u expected %p, got %p\n",
                     dr, _p(exp), _p(got));
 }
 
+static void check_init_msr(const char *name, uint64_t exp, uint64_t got)
+{
+    if ( got != exp )
+        xtf_failure("  Fail: %s expected %08"PRIx64", got %08"PRIx64"\n",
+                    name, exp, got);
+}
+
 static void test_initial_debug_state(void)
 {
     printk("Test initial debug state\n");
@@ -58,17 +64,22 @@ static void test_initial_debug_state(void)
     if ( read_cr4() & X86_CR4_DE )
         xtf_failure("  Fail: %%cr4.de expected to be clear\n");
 
-    check_initial_state(0, 0, read_dr0());
-    check_initial_state(1, 0, read_dr1());
-    check_initial_state(2, 0, read_dr2());
-    check_initial_state(3, 0, read_dr3());
-    check_initial_state(6, X86_DR6_DEFAULT, read_dr6());
-    check_initial_state(7, X86_DR7_DEFAULT, read_dr7());
-
-    uint64_t val;
-    if ( (val = rdmsr(MSR_DEBUGCTL)) != 0 )
-         xtf_failure("  Fail: MSR_DEBUGCTL expected %08x, got %08"PRIx64"\n",
-                     0, val);
+    check_init_dr(0, 0, read_dr0());
+    check_init_dr(1, 0, read_dr1());
+    check_init_dr(2, 0, read_dr2());
+    check_init_dr(3, 0, read_dr3());
+    check_init_dr(6, X86_DR6_DEFAULT, read_dr6());
+    check_init_dr(7, X86_DR7_DEFAULT, read_dr7());
+
+    check_init_msr("MSR_DEBUGCTL", 0, rdmsr(MSR_DEBUGCTL));
+
+    if ( cpu_has_dbext )
+    {
+        check_init_msr("MSR_DR0_ADDR_MASK", 0, rdmsr(MSR_DR0_ADDR_MASK));
+        check_init_msr("MSR_DR1_ADDR_MASK", 0, rdmsr(MSR_DR1_ADDR_MASK));
+        check_init_msr("MSR_DR2_ADDR_MASK", 0, rdmsr(MSR_DR2_ADDR_MASK));
+        check_init_msr("MSR_DR3_ADDR_MASK", 0, rdmsr(MSR_DR3_ADDR_MASK));
+    }
 }
 
 /*