From: Paolo Bonzini <pbonzini@redhat.com>
Date: Wed, 13 Nov 2019 14:54:35 +0000 (+0100)
Subject: target/i386: add PSCHANGE_NO bit for the ARCH_CAPABILITIES MSR
X-Git-Tag: qemu-xen-4.14.0~268^2~9
X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=7f7a585d5bd3c7f1275d28c77d9d67513c1de36c;p=qemu-xen.git

target/i386: add PSCHANGE_NO bit for the ARCH_CAPABILITIES MSR

This is required to disable ITLB multihit mitigations in nested
hypervisors.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index a624163ac2..2f60df37c4 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1204,7 +1204,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
         .type = MSR_FEATURE_WORD,
         .feat_names = {
             "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
-            "ssb-no", "mds-no", NULL, NULL,
+            "ssb-no", "mds-no", "pschange-mc-no", NULL,
             NULL, NULL, NULL, NULL,
             NULL, NULL, NULL, NULL,
             NULL, NULL, NULL, NULL,