From: Peter Maydell Date: Thu, 20 May 2021 15:28:35 +0000 (+0100) Subject: target/arm: Add MVE check to VMOV_reg_sp and VMOV_reg_dp X-Git-Tag: qemu-xen-4.16.0-rc4~138^2~41 X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=7e435b9ea645b370aa32364fa22f8e4cd9e7d9ec;p=qemu-xen.git target/arm: Add MVE check to VMOV_reg_sp and VMOV_reg_dp Split out the handling of VMOV_reg_sp and VMOV_reg_dp so that we can permit the insns if either FP or MVE are present. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210520152840.24453-5-peter.maydell@linaro.org --- diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 89246a284a..ac5832a4ed 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -2818,8 +2818,19 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a) return do_vfp_2op_##PREC(s, FN, a->vd, a->vm); \ } -DO_VFP_2OP(VMOV_reg, sp, tcg_gen_mov_i32, aa32_fpsp_v2) -DO_VFP_2OP(VMOV_reg, dp, tcg_gen_mov_i64, aa32_fpdp_v2) +#define DO_VFP_VMOV(INSN, PREC, FN) \ + static bool trans_##INSN##_##PREC(DisasContext *s, \ + arg_##INSN##_##PREC *a) \ + { \ + if (!dc_isar_feature(aa32_fp##PREC##_v2, s) && \ + !dc_isar_feature(aa32_mve, s)) { \ + return false; \ + } \ + return do_vfp_2op_##PREC(s, FN, a->vd, a->vm); \ + } + +DO_VFP_VMOV(VMOV_reg, sp, tcg_gen_mov_i32) +DO_VFP_VMOV(VMOV_reg, dp, tcg_gen_mov_i64) DO_VFP_2OP(VABS, hp, gen_helper_vfp_absh, aa32_fp16_arith) DO_VFP_2OP(VABS, sp, gen_helper_vfp_abss, aa32_fpsp_v2)