From: Andrew Cooper Date: Mon, 13 Nov 2017 15:41:38 +0000 (+0000) Subject: x86/cpuid: Offer Indirect Branch Controls to guests X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=67c6838ddacfa646f9d1ae802bd0f16a935665b8;p=people%2Fdariof%2Fxen.git x86/cpuid: Offer Indirect Branch Controls to guests With all infrastructure in place, it is now safe to let guests see and use these features. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich Acked-by: Wei Liu --- diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index 0f21fed161..fa81af14b7 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -237,13 +237,13 @@ XEN_CPUFEATURE(EFRO, 7*32+10) /* APERF/MPERF Read Only interface */ /* AMD-defined CPU features, CPUID level 0x80000008.ebx, word 8 */ XEN_CPUFEATURE(CLZERO, 8*32+ 0) /*A CLZERO instruction */ -XEN_CPUFEATURE(IBPB, 8*32+12) /* IBPB support only (no IBRS, used by AMD) */ +XEN_CPUFEATURE(IBPB, 8*32+12) /*A IBPB support only (no IBRS, used by AMD) */ /* Intel-defined CPU features, CPUID level 0x00000007:0.edx, word 9 */ XEN_CPUFEATURE(AVX512_4VNNIW, 9*32+ 2) /*A AVX512 Neural Network Instructions */ XEN_CPUFEATURE(AVX512_4FMAPS, 9*32+ 3) /*A AVX512 Multiply Accumulation Single Precision */ -XEN_CPUFEATURE(IBRSB, 9*32+26) /* IBRS and IBPB support (used by Intel) */ -XEN_CPUFEATURE(STIBP, 9*32+27) /*! STIBP */ +XEN_CPUFEATURE(IBRSB, 9*32+26) /*A IBRS and IBPB support (used by Intel) */ +XEN_CPUFEATURE(STIBP, 9*32+27) /*A! STIBP */ #endif /* XEN_CPUFEATURE */