From: Stefan Weil <sw@weilnetz.de>
Date: Sun, 9 Apr 2023 20:18:28 +0000 (+0200)
Subject: docs/cxl: Fix sentence
X-Git-Tag: pull-xen-20230607~110^2~20
X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=63cec0506e32467ec94db2973a9459147f081abf;p=people%2Faperard%2Fqemu-dm.git

docs/cxl: Fix sentence

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Message-Id: <20230409201828.1159568-1-sw@weilnetz.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
---

diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
index f25783a4ec..4c38223069 100644
--- a/docs/system/devices/cxl.rst
+++ b/docs/system/devices/cxl.rst
@@ -111,7 +111,7 @@ Interfaces provided include:
 
 CXL Root Ports (CXL RP)
 ~~~~~~~~~~~~~~~~~~~~~~~
-A CXL Root Port servers te same purpose as a PCIe Root Port.
+A CXL Root Port serves the same purpose as a PCIe Root Port.
 There are a number of CXL specific Designated Vendor Specific
 Extended Capabilities (DVSEC) in PCIe Configuration Space
 and associated component register access via PCI bars.