From: Andrew Cooper <andrew.cooper3@citrix.com>
Date: Fri, 23 Mar 2018 13:17:05 +0000 (+0000)
Subject: Factor out debug register infrastructure into a new header
X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=5c4c7fc69eafa39805b857c4c40840d2dc2e9b41;p=people%2Fandrewcoop%2Fxen-test-framework.git

Factor out debug register infrastructure into a new header

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
---

diff --git a/arch/x86/include/arch/lib.h b/arch/x86/include/arch/lib.h
index 6714bdc..0045902 100644
--- a/arch/x86/include/arch/lib.h
+++ b/arch/x86/include/arch/lib.h
@@ -211,24 +211,6 @@ static inline void write_ss(unsigned int ss)
     asm volatile ("mov %0, %%ss" :: "r" (ss));
 }
 
-static inline unsigned long read_dr6(void)
-{
-    unsigned long val;
-
-    asm volatile ("mov %%dr6, %0" : "=r" (val));
-
-    return val;
-}
-
-static inline unsigned long read_dr7(void)
-{
-    unsigned long val;
-
-    asm volatile ("mov %%dr7, %0" : "=r" (val));
-
-    return val;
-}
-
 static inline unsigned long read_cr0(void)
 {
     unsigned long cr0;
diff --git a/arch/x86/include/arch/processor.h b/arch/x86/include/arch/processor.h
index 2059cfc..0c33545 100644
--- a/arch/x86/include/arch/processor.h
+++ b/arch/x86/include/arch/processor.h
@@ -61,17 +61,6 @@
 #define X86_CR4_SMEP            0x00100000  /* SMEP                           */
 #define X86_CR4_SMAP            0x00200000  /* SMAP                           */
 
-/*
- * DR6 status bits.
- */
-#define X86_DR6_B0              (1u <<  0)  /* Breakpoint 0 triggered  */
-#define X86_DR6_B1              (1u <<  1)  /* Breakpoint 1 triggered  */
-#define X86_DR6_B2              (1u <<  2)  /* Breakpoint 2 triggered  */
-#define X86_DR6_B3              (1u <<  3)  /* Breakpoint 3 triggered  */
-#define X86_DR6_BD              (1u << 13)  /* Debug register accessed */
-#define X86_DR6_BS              (1u << 14)  /* Single step             */
-#define X86_DR6_BT              (1u << 15)  /* Task switch             */
-
 /*
  * CPU features in XCR0.
  */
diff --git a/arch/x86/include/arch/x86-dbg-reg.h b/arch/x86/include/arch/x86-dbg-reg.h
new file mode 100644
index 0000000..353bb2f
--- /dev/null
+++ b/arch/x86/include/arch/x86-dbg-reg.h
@@ -0,0 +1,49 @@
+/**
+ * @file arch/x86/include/arch/x86-dbg-reg.h
+ *
+ * %x86 Debug Register Infrastructure
+ */
+
+#ifndef XTF_X86_DBG_REG_H
+#define XTF_X86_DBG_REG_H
+
+/*
+ * DR6 status bits.
+ */
+#define X86_DR6_B0              (1u <<  0)  /* Breakpoint 0 triggered  */
+#define X86_DR6_B1              (1u <<  1)  /* Breakpoint 1 triggered  */
+#define X86_DR6_B2              (1u <<  2)  /* Breakpoint 2 triggered  */
+#define X86_DR6_B3              (1u <<  3)  /* Breakpoint 3 triggered  */
+#define X86_DR6_BD              (1u << 13)  /* Debug register accessed */
+#define X86_DR6_BS              (1u << 14)  /* Single step             */
+#define X86_DR6_BT              (1u << 15)  /* Task switch             */
+
+static inline unsigned long read_dr6(void)
+{
+    unsigned long val;
+
+    asm volatile ("mov %%dr6, %0" : "=r" (val));
+
+    return val;
+}
+
+static inline unsigned long read_dr7(void)
+{
+    unsigned long val;
+
+    asm volatile ("mov %%dr7, %0" : "=r" (val));
+
+    return val;
+}
+
+#endif /* XTF_X86_DBG_REG_H */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * tab-width: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/arch/x86/include/arch/xtf.h b/arch/x86/include/arch/xtf.h
index c9b9b89..2956e1a 100644
--- a/arch/x86/include/arch/xtf.h
+++ b/arch/x86/include/arch/xtf.h
@@ -10,6 +10,7 @@
 #include <arch/msr.h>
 #include <arch/pagetable.h>
 #include <arch/symbolic-const.h>
+#include <arch/x86-dbg-reg.h>
 
 extern char _end[];