From: Ross Philipson <ross.philipson@citrix.com>
Date: Fri, 27 Mar 2009 22:13:26 +0000 (-0400)
Subject: FLR - intermediate checkin 9 3/27 - fixed reg write byte, added
X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=49c6405bb83df772a397229d6ad22c334f8dbad7;p=xenclient%2Fkernel.git

FLR - intermediate checkin 9 3/27 - fixed reg write byte, added
some dbg tracing.

 Changes to be committed:
	modified:   drivers/xen/pciback/pciback_ops.c
---

diff --git a/drivers/xen/pciback/pciback_ops.c b/drivers/xen/pciback/pciback_ops.c
index 2d205a20..1c74b0b1 100644
--- a/drivers/xen/pciback/pciback_ops.c
+++ b/drivers/xen/pciback/pciback_ops.c
@@ -84,6 +84,8 @@ void pciback_reset_device(struct pci_dev *dev)
 static void pciback_do_pcie_flr(struct pci_dev *dev, int exp_pos)
 {
 	u16 status;
+	
+	dev_dbg(&dev->dev, "doing PCIe FLR\n");	
 
 	pci_block_user_cfg_access(dev);
 
@@ -114,6 +116,8 @@ static void pciback_do_pci_flr(struct pci_dev *dev, int af_pos)
 {
 	u8 status;
 
+	dev_dbg(&dev->dev, "doing PCI FLR\n");
+
 	pci_block_user_cfg_access(dev);
 
 	/* Clear the command register to prevent new transactions */
@@ -130,7 +134,7 @@ static void pciback_do_pci_flr(struct pci_dev *dev, int af_pos)
 			dev_warn(&dev->dev, "Still busy after 1s; proceeding with reset anyway\n");
 	}
 
-	pci_write_config_word(dev, af_pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
+	pci_write_config_byte(dev, af_pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
 	mdelay(200);
 
 	pciback_reload_config_space(dev);
@@ -149,7 +153,9 @@ static int pciback_do_vendor_specific_reset(struct pci_dev *dev)
 	u32 reg32;
 	u16 vendor_id, device_id, class_id;	
 	u8 reg8;
-	
+
+	dev_dbg(&dev->dev, "doing vendor specific resets\n");	
+
 	pci_read_config_word(dev, PCI_VENDOR_ID, &vendor_id);
 	if (vendor_id != PCIBACK_VENDOR_INTEL)
 		return -ENXIO;
@@ -228,6 +234,8 @@ static int pciback_do_dstate_transition_reset(struct pci_dev *dev)
 	if (pm_pos == 0)
 		return -ENXIO;
 
+	dev_dbg(&dev->dev, "doing Dstate transition reset\n");	
+
 	/* No_Soft_Reset - When set 1, this bit indicates that devices
 	 * transitioning from D3hot to D0 because of PowerState commands 
 	 * do not perform an internal reset.
@@ -269,6 +277,8 @@ static int pciback_do_secondary_bus_reset(struct pci_dev *dev)
 	int i = 0;
 	int err = 0;
 
+	dev_dbg(&dev->dev, "doing PCIe secondary bus reset\n");	
+
 	/* Enumerate all devices that share the same slot for the
 	 * multifunction device case.
 	 */