From: Nathan Egge Date: Thu, 3 Aug 2023 13:14:24 +0000 (-0400) Subject: linux-user/elfload: Set V in ELF_HWCAP for RISC-V X-Git-Tag: qemu-xen-4.20.0~596^2~9 X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=4333f0924c2f2ca8efaebaed8c24f55f77d8b013;p=qemu-xen.git linux-user/elfload: Set V in ELF_HWCAP for RISC-V Set V bit for hwcap if misa is set. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1793 Signed-off-by: Nathan Egge Reviewed-by: Daniel Henrique Barboza Tested-by: Daniel Henrique Barboza Message-Id: <20230803131424.40744-1-negge@xiph.org> Signed-off-by: Richard Henderson --- diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 861ec07abc..a299ba7300 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1710,7 +1710,8 @@ static uint32_t get_elf_hwcap(void) #define MISA_BIT(EXT) (1 << (EXT - 'A')) RISCVCPU *cpu = RISCV_CPU(thread_cpu); uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A') - | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C'); + | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C') + | MISA_BIT('V'); return cpu->env.misa_ext & mask; #undef MISA_BIT