From: Richard Henderson <rth@twiddle.net>
Date: Tue, 22 Nov 2016 15:53:53 +0000 (+0100)
Subject: target-alpha: Fix interrupt mask for cpu1
X-Git-Tag: qemu-xen-4.9.0-rc1~40^2
X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=424ad8388f89f4202a7836d003273f23ebe04b09;p=qemu-xen.git

target-alpha: Fix interrupt mask for cpu1

A typo prevents ISA interrupts from being recognized on cpu0,
which is where the smp kernel normally wants to see them.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---

diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c
index 883db13f96..f50f5cf186 100644
--- a/hw/alpha/typhoon.c
+++ b/hw/alpha/typhoon.c
@@ -376,7 +376,7 @@ static void cchip_write(void *opaque, hwaddr addr,
         break;
     case 0x0240: /* DIM1 */
         /* DIM: Device Interrupt Mask Register, CPU1.  */
-        s->cchip.dim[0] = val;
+        s->cchip.dim[1] = val;
         cpu_irq_change(s->cchip.cpu[1], val & s->cchip.drir);
         break;