From: Ross Philipson Date: Wed, 25 Mar 2009 12:22:18 +0000 (-0400) Subject: FLR - intermediate checkin 3/25 X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=3e854ef785b031a74e9fbc19ea9c412f3c5507ae;p=xenclient%2Fkernel.git FLR - intermediate checkin 3/25 Changes to be committed: modified: drivers/xen/pciback/controller.c modified: drivers/xen/pciback/passthrough.c modified: drivers/xen/pciback/pci_stub.c modified: drivers/xen/pciback/pciback.h modified: drivers/xen/pciback/pciback_ops.c modified: drivers/xen/pciback/slot.c modified: drivers/xen/pciback/vpci.c modified: include/linux/pci_ids.h modified: include/linux/pci_regs.h --- diff --git a/drivers/xen/pciback/controller.c b/drivers/xen/pciback/controller.c index 20e45a41..671386ff 100644 --- a/drivers/xen/pciback/controller.c +++ b/drivers/xen/pciback/controller.c @@ -208,7 +208,7 @@ void pciback_release_pci_dev(struct pciback_device *pdev, struct pci_dev *dev) } spin_unlock_irqrestore(&dev_data->lock, flags); - pcistub_put_pci_dev(found_dev); + pcistub_put_pci_dev(found_dev, 0); } int pciback_init_devices(struct pciback_device *pdev) @@ -396,7 +396,7 @@ void pciback_release_devices(struct pciback_device *pdev) list_for_each_entry_safe(dev_entry, d, &cntrl_entry->dev_list, list) { list_del(&dev_entry->list); - pcistub_put_pci_dev(dev_entry->dev); + pcistub_put_pci_dev(dev_entry->dev, 0); kfree(dev_entry); } list_del(&cntrl_entry->list); diff --git a/drivers/xen/pciback/passthrough.c b/drivers/xen/pciback/passthrough.c index 73b53906..b8cfbd74 100644 --- a/drivers/xen/pciback/passthrough.c +++ b/drivers/xen/pciback/passthrough.c @@ -88,7 +88,7 @@ void pciback_release_pci_dev(struct pciback_device *pdev, struct pci_dev *dev) spin_unlock_irqrestore(&dev_data->lock, flags); if (found_dev) - pcistub_put_pci_dev(found_dev); + pcistub_put_pci_dev(found_dev, 1); } int pciback_init_devices(struct pciback_device *pdev) @@ -157,7 +157,7 @@ void pciback_release_devices(struct pciback_device *pdev) list_for_each_entry_safe(dev_entry, t, &dev_data->dev_list, list) { list_del(&dev_entry->list); - pcistub_put_pci_dev(dev_entry->dev); + pcistub_put_pci_dev(dev_entry->dev, 1); kfree(dev_entry); } diff --git a/drivers/xen/pciback/pci_stub.c b/drivers/xen/pciback/pci_stub.c index 155ad6dd..bc6af30b 100644 --- a/drivers/xen/pciback/pci_stub.c +++ b/drivers/xen/pciback/pci_stub.c @@ -15,7 +15,16 @@ #include "conf_space_quirks.h" static char *pci_devs_to_hide = NULL; -module_param_named(hide, pci_devs_to_hide, charp, 0444); +module_param_named(hide, pci_devs_to_hide, charp, S_IRUGO); + +static int disable_flr = 0; +module_param_named(noflr, disable_flr, int, S_IRUGO); + +static char *pci_devs_use_sbr = NULL; +module_param_named(sbr, pci_devs_use_sbr, charp, S_IRUGO); + +static char *pci_devs_use_d3r = NULL; +module_param_named(d3r, pci_devs_use_d3r, charp, S_IRUGO); struct pcistub_device_id { struct list_head slot_list; @@ -26,6 +35,11 @@ struct pcistub_device_id { static LIST_HEAD(pcistub_device_ids); static DEFINE_SPINLOCK(device_ids_lock); +/* reset usage lists */ +static LIST_HEAD(pcistub_sbr_device_ids); +static LIST_HEAD(pcistub_d3r_device_ids); +static DEFINE_SPINLOCK(device_reset_ids_lock); + struct pcistub_device { struct kref kref; struct list_head dev_list; @@ -69,6 +83,23 @@ static struct pcistub_device *pcistub_device_alloc(struct pci_dev *dev) return psdev; } +static struct pciback_dev_data *pcistub_dev_data_alloc(struct pci_dev *dev) +{ + struct pciback_dev_data *dev_data; + + dev_dbg(&dev->dev, "pcistub_dev_data_alloc\n"); + + dev_data = kzalloc(sizeof(*dev_data) + dev->cfg_size, GFP_ATOMIC); + if (!dev_data) + return NULL; + + pci_set_drvdata(dev, dev_data); + + dev_data->cfg_space = (u8*)(dev_data) + sizeof(*dev_data); + + return dev_data; +} + /* Don't call this directly as it's called by pcistub_device_put */ static void pcistub_device_release(struct kref *kref) { @@ -121,7 +152,7 @@ static struct pcistub_device *pcistub_device_find(int domain, int bus, /* didn't find it */ psdev = NULL; - out: +out: spin_unlock_irqrestore(&pcistub_devices_lock, flags); return psdev; } @@ -191,7 +222,7 @@ struct pci_dev *pcistub_get_pci_dev(struct pciback_device *pdev, return found_dev; } -void pcistub_put_pci_dev(struct pci_dev *dev) +void pcistub_put_pci_dev(struct pci_dev *dev, int do_flr) { struct pcistub_device *psdev, *found_psdev = NULL; unsigned long flags; @@ -207,6 +238,12 @@ void pcistub_put_pci_dev(struct pci_dev *dev) spin_unlock_irqrestore(&pcistub_devices_lock, flags); + /* For pass-through devices, do an FLR (or approximate) for the device + * before it is put back and ready for the next domain + */ + if (!disable_flr && do_flr) + pciback_flr_device(dev); + /* Cleanup our device * (so it's ready for the next domain) */ @@ -221,6 +258,43 @@ void pcistub_put_pci_dev(struct pci_dev *dev) pcistub_device_put(found_psdev); } +struct pci_dev *pcistub_ref_pci_dev(struct pci_dev *dev) +{ + struct pcistub_device *psdev; + struct pci_dev *found_dev = NULL; + unsigned long flags; + + spin_lock_irqsave(&pcistub_devices_lock, flags); + + list_for_each_entry(psdev, &pcistub_devices, dev_list) { + if (psdev->dev == dev) { + pcistub_device_get(psdev); /* just a ref count */ + found_dev = psdev->dev; + break; + } + } + + spin_unlock_irqrestore(&pcistub_devices_lock, flags); + return found_dev; +} + +void pcistub_unref_pci_dev(struct pci_dev *dev) +{ + struct pcistub_device *psdev; + unsigned long flags; + + spin_lock_irqsave(&pcistub_devices_lock, flags); + + list_for_each_entry(psdev, &pcistub_devices, dev_list) { + if (psdev->dev == dev) { + pcistub_device_get(psdev); /* just an unref count */ + break; + } + } + + spin_unlock_irqrestore(&pcistub_devices_lock, flags); +} + static int __devinit pcistub_match_one(struct pci_dev *dev, struct pcistub_device_id *pdev_id) { @@ -241,20 +315,26 @@ static int __devinit pcistub_match_one(struct pci_dev *dev, return 0; } -static int __devinit pcistub_match(struct pci_dev *dev) +static int __devinit pcistub_match(struct pci_dev *dev, struct list_head *list) { struct pcistub_device_id *pdev_id; unsigned long flags; int found = 0; + spinlock_t *lock; - spin_lock_irqsave(&device_ids_lock, flags); - list_for_each_entry(pdev_id, &pcistub_device_ids, slot_list) { + if (list == &pcistub_device_ids) + lock = &device_ids_lock; + else + lock = &device_reset_ids_lock; + + spin_lock_irqsave(lock, flags); + list_for_each_entry(pdev_id, list, slot_list) { if (pcistub_match_one(dev, pdev_id)) { found = 1; break; } } - spin_unlock_irqrestore(&device_ids_lock, flags); + spin_unlock_irqrestore(lock, flags); return found; } @@ -271,12 +351,11 @@ static int __devinit pcistub_init_device(struct pci_dev *dev) * would need to be called somewhere to free the memory allocated * here and then to call kfree(pci_get_drvdata(psdev->dev)). */ - dev_data = kzalloc(sizeof(*dev_data), GFP_ATOMIC); + dev_data = pcistub_dev_data_alloc(dev); if (!dev_data) { err = -ENOMEM; goto out; } - pci_set_drvdata(dev, dev_data); dev_dbg(&dev->dev, "initializing config\n"); err = pciback_config_init_dev(dev); @@ -301,12 +380,25 @@ static int __devinit pcistub_init_device(struct pci_dev *dev) dev_dbg(&dev->dev, "reset device\n"); pciback_reset_device(dev); + /* Classify the device so we know if it is PCI/PCIe and if it is + * a bridge - this information is used for FLR logic. Also store + * values if SBR/D3R reset logic was requested. + */ + pciback_classify_device(dev); + dev_data->use_sbr = pcistub_match(dev, &pcistub_sbr_device_ids); + dev_data->use_d3r = pcistub_match(dev, &pcistub_d3r_device_ids); + + /* Store the config space here where the device is off and ready to be + * exported before any FLRs or other resets are done + */ + pciback_store_config_space(dev); + return 0; - config_release: +config_release: pciback_config_free_dev(dev); - out: +out: pci_set_drvdata(dev, NULL); kfree(dev_data); return err; @@ -398,7 +490,7 @@ static int __devinit pcistub_probe(struct pci_dev *dev, dev_dbg(&dev->dev, "probing...\n"); - if (pcistub_match(dev)) { + if (pcistub_match(dev, &pcistub_device_ids)) { if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL && dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { @@ -415,7 +507,7 @@ static int __devinit pcistub_probe(struct pci_dev *dev, /* Didn't find the device */ err = -ENODEV; - out: +out: return err; } @@ -606,10 +698,78 @@ static int pcistub_reg_add(int domain, int bus, int slot, int func, int reg, err = pciback_config_quirks_add_field(dev, field); if (err) kfree(field); - out: +out: + return err; +} + +static int pcistub_device_do_flr(int domain, int bus, int slot, int func) +{ + int err = 0; + struct pcistub_device *psdev; + struct pci_dev *dev; + + psdev = pcistub_device_find(domain, bus, slot, func); + if (!psdev || !psdev->dev) { + err = -ENODEV; + goto out; + } + dev = psdev->dev; + + /* Do an FLR (or approximate) for the device on demand and + * reload config + */ + pciback_flr_device(dev); + +out: return err; } +static int pcistub_device_id_sbr_add(int domain, int bus, int slot, int func) +{ + struct pcistub_device_id *pci_dev_id; + unsigned long flags; + + pci_dev_id = kmalloc(sizeof(*pci_dev_id), GFP_KERNEL); + if (!pci_dev_id) + return -ENOMEM; + + pci_dev_id->domain = domain; + pci_dev_id->bus = bus; + pci_dev_id->devfn = PCI_DEVFN(slot, func); + + pr_debug("pciback: adding sbr device %04x:%02x:%02x.%01x\n", + domain, bus, slot, func); + + spin_lock_irqsave(&device_reset_ids_lock, flags); + list_add_tail(&pci_dev_id->slot_list, &pcistub_sbr_device_ids); + spin_unlock_irqrestore(&device_reset_ids_lock, flags); + + return 0; +} + +static int pcistub_device_id_d3r_add(int domain, int bus, int slot, int func) +{ + struct pcistub_device_id *pci_dev_id; + unsigned long flags; + + pci_dev_id = kmalloc(sizeof(*pci_dev_id), GFP_KERNEL); + if (!pci_dev_id) + return -ENOMEM; + + pci_dev_id->domain = domain; + pci_dev_id->bus = bus; + pci_dev_id->devfn = PCI_DEVFN(slot, func); + + pr_debug("pciback: adding d3r device %04x:%02x:%02x.%01x\n", + domain, bus, slot, func); + + spin_lock_irqsave(&device_reset_ids_lock, flags); + list_add_tail(&pci_dev_id->slot_list, &pcistub_d3r_device_ids); + spin_unlock_irqrestore(&device_reset_ids_lock, flags); + + return 0; +} + static ssize_t pcistub_slot_add(struct device_driver *drv, const char *buf, size_t count) { @@ -622,7 +782,7 @@ static ssize_t pcistub_slot_add(struct device_driver *drv, const char *buf, err = pcistub_device_id_add(domain, bus, slot, func); - out: +out: if (!err) err = count; return err; @@ -642,7 +802,7 @@ static ssize_t pcistub_slot_remove(struct device_driver *drv, const char *buf, err = pcistub_device_id_remove(domain, bus, slot, func); - out: +out: if (!err) err = count; return err; @@ -687,7 +847,7 @@ static ssize_t pcistub_quirk_add(struct device_driver *drv, const char *buf, err = pcistub_reg_add(domain, bus, slot, func, reg, size, mask); - out: +out: if (!err) err = count; return err; @@ -731,7 +891,7 @@ static ssize_t pcistub_quirk_show(struct device_driver *drv, char *buf) } } - out: +out: spin_unlock_irqrestore(&device_ids_lock, flags); return count; @@ -739,7 +899,7 @@ static ssize_t pcistub_quirk_show(struct device_driver *drv, char *buf) DRIVER_ATTR(quirks, S_IRUSR | S_IWUSR, pcistub_quirk_show, pcistub_quirk_add); -static ssize_t permissive_add(struct device_driver *drv, const char *buf, +static ssize_t pcistub_permissive_add(struct device_driver *drv, const char *buf, size_t count) { int domain, bus, slot, func; @@ -772,15 +932,15 @@ static ssize_t permissive_add(struct device_driver *drv, const char *buf, dev_warn(&psdev->dev->dev, "permissive mode is potentially unsafe!\n"); } - release: +release: pcistub_device_put(psdev); - out: +out: if (!err) err = count; return err; } -static ssize_t permissive_show(struct device_driver *drv, char *buf) +static ssize_t pcistub_permissive_show(struct device_driver *drv, char *buf) { struct pcistub_device *psdev; struct pciback_dev_data *dev_data; @@ -803,7 +963,62 @@ static ssize_t permissive_show(struct device_driver *drv, char *buf) return count; } -DRIVER_ATTR(permissive, S_IRUSR | S_IWUSR, permissive_show, permissive_add); +DRIVER_ATTR(permissive, S_IRUSR | S_IWUSR, pcistub_permissive_show, pcistub_permissive_add); + +static ssize_t pcistub_do_flr(struct device_driver *drv, const char *buf, + size_t count) +{ + int domain, bus, slot, func; + int err; + + err = str_to_slot(buf, &domain, &bus, &slot, &func); + if (err) + goto out; + + err = pcistub_device_do_flr(domain, bus, slot, func); + +out: + if (!err) + err = count; + return err; +} + +DRIVER_ATTR(do_flr, S_IWUSR, NULL, pcistub_do_flr); + +static ssize_t pcistub_resets(struct device_driver *drv, const char *buf, + size_t count) +{ + int domain, bus, slot, func; + int is_sbr, err; + + /* string begins with reset type specifier sbr=|dr3= */ + if (!strncmp(buf, "sbr=", 4)) { + is_sbr = 1; + buf += 4; + } else if (!strncmp(buf, "d3r=", 4)) { + is_sbr = 0; + buf += 4; + } else { + err = -EINVAL; + goto out; + } + + err = str_to_slot(buf, &domain, &bus, &slot, &func); + if (err) + goto out; + + if (is_sbr) + err = pcistub_device_id_sbr_add(domain, bus, slot, func); + else + err = pcistub_device_id_d3r_add(domain, bus, slot, func); + +out: + if (!err) + err = count; + return err; +} + +DRIVER_ATTR(resets, S_IWUSR, NULL, pcistub_resets); #ifdef CONFIG_PCI_MSI @@ -829,6 +1044,8 @@ static void pcistub_exit(void) driver_remove_file(&pciback_pci_driver.driver, &driver_attr_slots); driver_remove_file(&pciback_pci_driver.driver, &driver_attr_quirks); driver_remove_file(&pciback_pci_driver.driver, &driver_attr_permissive); + driver_remove_file(&pciback_pci_driver.driver, &driver_attr_do_flr); + driver_remove_file(&pciback_pci_driver.driver, &driver_attr_resets); pci_unregister_driver(&pciback_pci_driver); WARN_ON(unregister_msi_get_owner(pciback_get_owner)); @@ -836,35 +1053,20 @@ static void pcistub_exit(void) static int __init pcistub_init(void) { - int pos = 0; int err = 0; - int domain, bus, slot, func; - int parsed; - - if (pci_devs_to_hide && *pci_devs_to_hide) { - do { - parsed = 0; - - err = sscanf(pci_devs_to_hide + pos, - " (%x:%x:%x.%x) %n", - &domain, &bus, &slot, &func, &parsed); - if (err != 4) { - domain = 0; - err = sscanf(pci_devs_to_hide + pos, - " (%x:%x.%x) %n", - &bus, &slot, &func, &parsed); - if (err != 3) - goto parse_error; - } - - err = pcistub_device_id_add(domain, bus, slot, func); - if (err) - goto out; - /* if parsed<=0, we've reached the end of the string */ - pos += parsed; - } while (parsed > 0 && pci_devs_to_hide[pos]); - } + /* Parse device lists for hide, sbr, and d3r */ + err = pciback_parse_device_params(pci_devs_to_hide, pcistub_device_id_add); + if (err) + goto out; + + err = pciback_parse_device_params(pci_devs_use_sbr, pcistub_device_id_sbr_add); + if (err) + goto out; + + err = pciback_parse_device_params(pci_devs_use_d3r, pcistub_device_id_d3r_add); + if (err) + goto out; /* If we're the first PCI Device Driver to register, we're the * first one to get offered PCI devices as they become @@ -888,19 +1090,20 @@ static int __init pcistub_init(void) if (!err) err = driver_create_file(&pciback_pci_driver.driver, &driver_attr_permissive); + if (!err) + err = driver_create_file(&pciback_pci_driver.driver, + &driver_attr_do_flr); + if (!err) + err = driver_create_file(&pciback_pci_driver.driver, + &driver_attr_resets); if (!err) err = register_msi_get_owner(pciback_get_owner); if (err) pcistub_exit(); - out: +out: return err; - - parse_error: - printk(KERN_ERR "pciback: Error parsing pci_devs_to_hide at \"%s\"\n", - pci_devs_to_hide + pos); - return -EINVAL; } #ifndef MODULE diff --git a/drivers/xen/pciback/pciback.h b/drivers/xen/pciback/pciback.h index b6ea8517..e908e7fa 100644 --- a/drivers/xen/pciback/pciback.h +++ b/drivers/xen/pciback/pciback.h @@ -23,6 +23,14 @@ struct pci_dev_entry { #define _PDEVF_op_active (0) #define PDEVF_op_active (1<<(_PDEVF_op_active)) +#define PCIBACK_TYPE_UNKNOWN 0 +#define PCIBACK_TYPE_PCIe_ENDPOINT 1 +#define PCIBACK_TYPE_PCIe_BRIDGE 2 +#define PCIBACK_TYPE_PCI_BRIDGE 3 +#define PCIBACK_TYPE_PCI 4 + +#define DEV_CLASS_PCI_PCI_BRIDGE 0x0604 + struct pciback_device { void *pci_dev_data; spinlock_t dev_lock; @@ -46,6 +54,12 @@ struct pciback_dev_data { struct list_head config_fields; int permissive; int warned_on_write; + u32 dev_type; + int exp_flr_offset; + int af_flr_offset; + int use_sbr; + int use_d3r; + u8 *cfg_space; /* saved config space for device */ }; /* Get/Put PCI Devices that are hidden from the PCI Backend Domain */ @@ -54,11 +68,25 @@ struct pci_dev *pcistub_get_pci_dev_by_slot(struct pciback_device *pdev, int slot, int func); struct pci_dev *pcistub_get_pci_dev(struct pciback_device *pdev, struct pci_dev *dev); -void pcistub_put_pci_dev(struct pci_dev *dev); +void pcistub_put_pci_dev(struct pci_dev *dev, int do_flr); + +/* Reference/unreference PCI Devices and stubs without changing the state */ +struct pci_dev *pcistub_ref_pci_dev(struct pci_dev *dev); +void pcistub_unref_pci_dev(struct pci_dev *dev); + +/* Store/reload config space for devices */ +void pciback_store_config_space(struct pci_dev *dev); +void pciback_reload_config_space(struct pci_dev *dev); /* Ensure a device is turned off or reset */ void pciback_reset_device(struct pci_dev *pdev); +/* Do a function level reset (or approximage functionality) for device */ +void pciback_flr_device(struct pci_dev *dev); + +/* Helper to classify the device type */ +void pciback_classify_device(struct pci_dev *dev); + /* Access a virtual configuration space for a PCI device */ int pciback_config_init(void); int pciback_config_init_dev(struct pci_dev *dev); @@ -90,6 +118,9 @@ void pciback_release_devices(struct pciback_device *pdev); irqreturn_t pciback_handle_event(int irq, void *dev_id, struct pt_regs *regs); void pciback_do_op(void *data); +/* Parse and load device specific module parameters */ +int pciback_parse_device_params(const char *device_args, int (*add_func) (int domain, int bus, int slot, int func)); + int pciback_xenbus_register(void); void pciback_xenbus_unregister(void); diff --git a/drivers/xen/pciback/pciback_ops.c b/drivers/xen/pciback/pciback_ops.c index 6c67a03e..09a027cb 100644 --- a/drivers/xen/pciback/pciback_ops.c +++ b/drivers/xen/pciback/pciback_ops.c @@ -4,6 +4,7 @@ * Author: Ryan Wilson */ #include +#include #include #include #include "pciback.h" @@ -11,6 +12,34 @@ int verbose_request = 0; module_param(verbose_request, int, 0644); +/* Used to store the config state so it can be restored after + * resets. + */ +void pciback_store_config_space(struct pci_dev *dev) +{ + struct pciback_dev_data *dev_data = pci_get_drvdata(dev); + u32 *ptr = (u32*)dev_data->cfg_space; + int i, count = dev->cfg_size/sizeof(u32); + + for (i = 0; i < count; i += sizeof(u32), ptr++) + pci_read_config_dword(dev, i, ptr); +} + +/* Used to reload the config state after resets. + */ +void pciback_reload_config_space(struct pci_dev *dev) +{ + struct pciback_dev_data *dev_data = pci_get_drvdata(dev); + u32 *ptr = (u32*)dev_data->cfg_space; + int i, val, count = dev->cfg_size/sizeof(u32); + + for (i = 0; i < count; i += sizeof(u32), ptr++) { + pci_read_config_dword(dev, i, &val); + if (val != *ptr) + pci_write_config_dword(dev, i, *ptr); + } +} + /* Ensure a device is "turned off" and ready to be exported. * (Also see pciback_config_reset to ensure virtual configuration space is * ready to be re-exported) @@ -38,6 +67,376 @@ void pciback_reset_device(struct pci_dev *dev) } } +/* Do a PCIe type function level reset for a single function on this + * device. + */ +static void pciback_do_pcie_flr(struct pci_dev *dev, int exp_pos) +{ + u16 status; + + pci_block_user_cfg_access(dev); + + /* Wait for Transaction Pending bit clean */ + msleep(100); + pci_read_config_word(dev, exp_pos + PCI_EXP_DEVSTA, &status); + if (status & PCI_EXP_DEVSTA_TRPND) { + dev_info(&dev->dev, "Busy after 100ms while trying to reset; sleeping for 1 second\n"); + ssleep(1); + pci_read_config_word(dev, exp_pos + PCI_EXP_DEVSTA, &status); + if (status & PCI_EXP_DEVSTA_TRPND) + dev_info(&dev->dev, "Still busy after 1s; proceeding with reset anyway\n"); + } + + pci_write_config_word(dev, exp_pos + PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); + mdelay(200); + + pciback_reload_config_space(dev); + + pci_unblock_user_cfg_access(dev); +} + +/* Do a PCI type function level reset for a single function on this + * device. This uses the Advanced Features Capability extensions to + * the PCI spec. + */ +static void pciback_do_pci_flr(struct pci_dev *dev, int af_pos) +{ + pci_block_user_cfg_access(dev); + + pci_write_config_word(dev, af_pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); + mdelay(200); + + pciback_reload_config_space(dev); + + pci_unblock_user_cfg_access(dev); +} + +/* Vendor specific resets. These can be set in the vendor specific + * capabilities structures. Currently only the Intel USB reset + * is supported. + */ +static int pciback_do_vendor_specific_reset(struct pci_dev *dev) +{ +#define PCIBACK_VENDOR_INTEL 0x8086 +#define PCIBACK_CLASS_ID_USB 0x0c03 +#define PCIBACK_USB_FLRCTRL 0x4 + int vendor_pos; + u16 vendor_id; + u16 class_id; + + vendor_pos = pci_find_capability(dev, PCI_CAP_ID_VNDR); + if (vendor_pos == 0) + return -ENXIO; + + pci_read_config_word(dev, PCI_VENDOR_ID, &vendor_id); + if (vendor_id != PCIBACK_VENDOR_INTEL) + return -ENXIO; + + pci_read_config_word(dev, PCI_CLASS_DEVICE, &class_id); + if (class_id != PCIBACK_CLASS_ID_USB) + return -ENXIO; + + pci_block_user_cfg_access(dev); + + pci_write_config_byte(dev, vendor_pos + PCIBACK_USB_FLRCTRL, 1); + mdelay(100); + + pciback_reload_config_space(dev); + + pci_unblock_user_cfg_access(dev); + + return 0; +} + +/* Use a D0-D3-D0 device state transition to reset the device. This + * is a good enough reset for some devices (like NICs). + */ +static int pciback_do_dstate_transition_reset(struct pci_dev *dev) +{ + int pm_pos; + u32 pm_ctl; + + pm_pos = pci_find_capability(dev, PCI_CAP_ID_PM); + if (pm_pos == 0) + return -ENXIO; + + /* No_Soft_Reset - When set 1, this bit indicates that devices + * transitioning from D3hot to D0 because of PowerState commands + * do not perform an internal reset. + */ + pci_read_config_dword(dev, pm_pos + PCI_PM_CTRL, &pm_ctl); + if (pm_ctl & PCI_PM_CTRL_NO_SOFT_RESET) + return -ENXIO; + + pci_block_user_cfg_access(dev); + + pm_ctl &= ~PCI_PM_CTRL_STATE_MASK; + pm_ctl |= PCI_PM_CTRL_D3HOT; + pci_write_config_word(dev, pm_pos + PCI_PM_CTRL, pm_ctl); + mdelay(10); + + pm_ctl &= ~PCI_PM_CTRL_STATE_MASK; + pm_ctl |= PCI_PM_CTRL_D0; + pci_write_config_word(dev, pm_pos + PCI_PM_CTRL, pm_ctl); + mdelay(10); + + pciback_reload_config_space(dev); + + pci_unblock_user_cfg_access(dev); + + return 0; +} + +/* Do a secondary bus reset on a bridge. This is only done if all + * co-assignment rules are satisfied or if it was explicitly + * requested via pciback parameters. Currently this is used only + * for PCIe devices where all the functions are co-assigned. + */ +static int pciback_do_secondary_bus_reset(struct pci_dev *dev) +{ + struct pci_dev *bridge = dev->bus->self; + u16 pci_bctl; + struct pci_dev *dev_tmp; + struct pci_dev *dev_arr[8]; + int i = 0; + int err = 0; + + /* Enumerate all devices that share the same slot for the + * multifunction device case. + */ + memset(dev_arr, 0, 8*sizeof(struct pci_dev*)); + dev_tmp = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, NULL); + while (dev_tmp != NULL) { + if (dev->bus->number == dev_tmp->bus->number && + PCI_SLOT(dev->devfn) == PCI_SLOT(dev_tmp->devfn)) { + + /* Check that the pciback driver owns the devices and get + * a reference so they can be reset. + */ + dev_arr[i] = pcistub_ref_pci_dev(dev_tmp); + if (dev_arr[i] == NULL) + goto failed; + + i++; + if (i == 8) { + pci_dev_put(dev_tmp); + break; + } + } + + dev_tmp = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev_tmp); + } + + pci_block_user_cfg_access(dev); + + /* Reset the bus and restore the PCI space for all the devfn found above. + */ + pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, &pci_bctl); + pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, pci_bctl | PCI_BRIDGE_CTL_BUS_RESET); + msleep(200); + pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, pci_bctl); + msleep(200); + + for (i = 0; i < 8; i++) { + if (dev_arr[i] != NULL) + pciback_reload_config_space(dev_arr[i]); + } + pciback_reload_config_space(dev); + + pci_unblock_user_cfg_access(dev); + + goto cleanup; + +failed: + err = -ENXIO + dev_warn(&dev->dev, + "secondary bus reset failed for device - all functions need to be co-assigned!\n"); + +cleanup: + for (i = 0; i < 8; i++) { + if (dev_arr[i] != NULL) + pcistub_unref_pci_dev(dev_arr[i]); + } + return err; +} + +/* This function is used to do a function level reset on a singe device/function. + * FLRs must be done on devices before they are unassigned from one domain and + * passed through to another. The preferred method is to do an actual FLR on the + * device but the functionality may not be present or exposed. In the later case + * we attempt to locate the capability even though it is not chained into the + * capabilities list. + * + * In some cases, there are no TODO... + */ +void pciback_flr_device(struct pci_dev *dev) +{ + struct pciback_dev_data *dev_data = pci_get_drvdata(dev); + int err = 0; + + if (dev_data->dev_type == PCIBACK_TYPE_PCIe_ENDPOINT) { + if (dev_data->exp_flr_offset != 0) { + pciback_do_pcie_flr(dev, dev_data->exp_flr_offset); + goto out; + } + + if (dev->bus->number == 0) { + err = pciback_do_vendor_specific_reset(dev); + if (err && dev_data->use_d3r) + err = pciback_do_dstate_transition_reset(dev); + if (err) { + dev_warn(&dev->dev, "FLR functionality not supported; " + "attempts to use vendor specific FLR and D-state transitions failed; " + "FLR not performed for device\n"); + } + + } + else if (dev_data->use_sbr) { + err = pciback_do_dstate_transition_reset(dev); + if (err) { + dev_warn(&dev->dev, "FLR functionality not supported; " + "attempts to use secondary bus reset failed; " + "FLR not performed for device\n"); + } + } + } + else if (dev_data->dev_type == PCIBACK_TYPE_PCI) { + if (dev_data->af_flr_offset != 0) { + pciback_do_pci_flr(dev, dev_data->af_flr_offset); + goto out; + } + if (dev->bus->number == 0) { + err = pciback_do_vendor_specific_reset(dev); + if (err && dev_data->use_d3r) + err = pciback_do_dstate_transition_reset(dev); + if (err) { + dev_warn(&dev->dev, "FLR functionality not supported; " + "attempts to use vendor specific FLR and D-state transitions failed; " + "FLR not performed for device\n"); + } + } + else { + dev_warn(&dev->dev, "FLR functionality not supported; " + "no secondary bus reset functionality available; " + "FLR not performed for device\n"); + } + } + else { + dev_warn(&dev->dev, + "FLR not being used for bridge devices.\n"); + } + + /* no return, trace warning about activity */ +out: +} + +/* Helper used to location the FLR capabilities for a PCIe device. + * When the capability cannot be found in the chain but is present, + * special logic is used to attempt to locate functionality. + * + * returns: the offset to the capability, zero if not found. + */ +static int pciback_find_pcie_flr_caps(struct pci_dev *dev) +{ + int exp_pos; + u32 cap; + + /* First look for the PCIe FLR capabilities using the capabilities list */ + exp_pos = pci_find_capability(dev, PCI_CAP_ID_EXP); + if (exp_pos) { + pci_read_config_dword(dev, exp_pos + PCI_EXP_DEVCAP, &cap); + if (cap & PCI_EXP_DEVCAP_FLR) { + return exp_pos; + } + } + + /* Next look for the unchained PCIe capabilities for FLR using specific logic */ + /* TODO */ + + /* Else not found */ + return 0; +} + +/* Helper used to location the AF FLR capabilities for a PCI device. + * When the capability cannot be found in the chain but is present, + * special logic is used to attempt to locate functionality. + * + * returns: the offset to the capability, zero if not found. + */ +static int pciback_find_pci_flr_caps(struct pci_dev *dev) +{ + int af_pos; + u8 cap; + + /* First look for the PCI AF capabilities for FLR using the capabilities list. This + * is only used on the devices on the root/host bus (integrated devices). + */ + if (dev->bus->number != 0) + return 0; + + af_pos = pci_find_capability(dev, PCI_CAP_ID_AF); + if (af_pos) { + pci_read_config_byte(dev, af_pos + PCI_AF_DEVCAP, &cap); + if (cap & PCI_EXP_DEVCAP_FLR) { + return af_pos; + } + } + + /* Next look for the unchained AF capabilities for FLR using specific logic */ + /* TODO */ + + /* Else not found */ + return 0; +} + +/* Classify the device, specifically determine if it is PCIe/PCI + * and whether it is a PCIe endpoint, bridge, or other PCI device. + */ +void pciback_classify_device(struct pci_dev *dev) +{ + struct pciback_dev_data *dev_data; + int err = 0; + u16 dev_class, exp_caps; + int exp_pos; + + dev_data = pci_get_drvdata(dev); + dev_data->dev_type = PCIBACK_TYPE_UNKNOWN; + + err = pci_read_config_word(dev, PCI_CLASS_DEVICE, &dev_class); + if (err) { + dev_warn(&dev->dev, "failed to read PCI class information!\n"); + goto classify_done; + } + exp_pos = pci_find_capability(dev, PCI_CAP_ID_EXP); + + if (dev_class != DEV_CLASS_PCI_PCI_BRIDGE) { + if (exp_pos != 0) { + dev_data->dev_type = PCIBACK_TYPE_PCIe_ENDPOINT; + dev_data->exp_flr_offset = pciback_find_pcie_flr_caps(dev); + } else { + dev_data->dev_type = PCIBACK_TYPE_PCI; + dev_data->af_flr_offset = pciback_find_pci_flr_caps(dev); + } + goto classify_done; + } + + if (exp_pos == 0) { + dev_data->dev_type = PCIBACK_TYPE_PCI_BRIDGE; + goto classify_done; + } + + err = pci_read_config_word(dev, exp_pos + PCI_EXP_FLAGS, &exp_caps); + if (err) { + dev_warn(&dev->dev, "failed to read PCI Express flags!\n"); + goto classify_done; + } + dev_data->dev_type = ((PCI_EXP_FLAGS_TYPE >> 4) == PCI_EXP_TYPE_PCI_BRIDGE) ? PCIBACK_TYPE_PCI_BRIDGE : PCIBACK_TYPE_PCIe_BRIDGE; + +classify_done: + + return; +} + static inline void test_and_schedule_op(struct pciback_device *pdev) { /* Check that frontend is requesting an operation and that we are not @@ -115,3 +514,44 @@ irqreturn_t pciback_handle_event(int irq, void *dev_id, struct pt_regs *regs) return IRQ_HANDLED; } + +int pciback_parse_device_params(const char *device_args, int (*add_func) (int domain, int bus, int slot, int func)) +{ + int pos = 0; + int err = 0; + int domain, bus, slot, func; + int parsed; + + if (device_args && *device_args) { + do { + parsed = 0; + + err = sscanf(device_args + pos, + " (%x:%x:%x.%x) %n", + &domain, &bus, &slot, &func, &parsed); + if (err != 4) { + domain = 0; + err = sscanf(device_args + pos, + " (%x:%x.%x) %n", + &bus, &slot, &func, &parsed); + if (err != 3) + goto parse_error; + } + + err = add_func(domain, bus, slot, func); + if (err) + goto out; + + /* if parsed<=0, we've reached the end of the string */ + pos += parsed; + } while (parsed > 0 && device_args[pos]); + } + +out: + return err; + +parse_error: + printk(KERN_ERR "pciback: Error parsing device parameters \"%s\" at \"%s\"\n", + device_args, device_args + pos); + return -EINVAL; +} \ No newline at end of file diff --git a/drivers/xen/pciback/slot.c b/drivers/xen/pciback/slot.c index 5a960926..eb95040b 100644 --- a/drivers/xen/pciback/slot.c +++ b/drivers/xen/pciback/slot.c @@ -109,7 +109,7 @@ void pciback_release_pci_dev(struct pciback_device *pdev, struct pci_dev *dev) spin_unlock_irqrestore(&slot_dev->lock, flags); if (found_dev) - pcistub_put_pci_dev(found_dev); + pcistub_put_pci_dev(found_dev, 0); } int pciback_init_devices(struct pciback_device *pdev) @@ -149,7 +149,7 @@ void pciback_release_devices(struct pciback_device *pdev) for (slot = 0; slot < PCI_SLOT_MAX; slot++) { dev = slot_dev->slots[bus][slot]; if (dev != NULL) - pcistub_put_pci_dev(dev); + pcistub_put_pci_dev(dev, 0); } kfree(slot_dev); diff --git a/drivers/xen/pciback/vpci.c b/drivers/xen/pciback/vpci.c index 09aa2e75..b8a507a9 100644 --- a/drivers/xen/pciback/vpci.c +++ b/drivers/xen/pciback/vpci.c @@ -162,7 +162,7 @@ void pciback_release_pci_dev(struct pciback_device *pdev, struct pci_dev *dev) spin_unlock_irqrestore(&vpci_dev->lock, flags); if (found_dev) - pcistub_put_pci_dev(found_dev); + pcistub_put_pci_dev(found_dev, 0); } int pciback_init_devices(struct pciback_device *pdev) @@ -202,7 +202,7 @@ void pciback_release_devices(struct pciback_device *pdev) list_for_each_entry_safe(e, tmp, &vpci_dev->dev_list[slot], list) { list_del(&e->list); - pcistub_put_pci_dev(e->dev); + pcistub_put_pci_dev(e->dev, 0); kfree(e); } } diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 9322ee61..d81bc132 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -15,8 +15,8 @@ #define PCI_CLASS_STORAGE_FLOPPY 0x0102 #define PCI_CLASS_STORAGE_IPI 0x0103 #define PCI_CLASS_STORAGE_RAID 0x0104 -#define PCI_CLASS_STORAGE_SATA 0x0106 -#define PCI_CLASS_STORAGE_SATA_AHCI 0x010601 +#define PCI_CLASS_STORAGE_SATA 0x0106 +#define PCI_CLASS_STORAGE_SATA_AHCI 0x010601 #define PCI_CLASS_STORAGE_SAS 0x0107 #define PCI_CLASS_STORAGE_OTHER 0x0180 @@ -97,7 +97,7 @@ #define PCI_BASE_CLASS_SERIAL 0x0c #define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 -#define PCI_CLASS_SERIAL_FIREWIRE_OHCI 0x0c0010 +#define PCI_CLASS_SERIAL_FIREWIRE_OHCI 0x0c0010 #define PCI_CLASS_SERIAL_ACCESS 0x0c01 #define PCI_CLASS_SERIAL_SSA 0x0c02 #define PCI_CLASS_SERIAL_USB 0x0c03 @@ -107,6 +107,10 @@ #define PCI_CLASS_SERIAL_FIBER 0x0c04 #define PCI_CLASS_SERIAL_SMBUS 0x0c05 +#define PCI_BASE_CLASS_WIRELESS 0x0d +#define PCI_CLASS_WIRELESS_RF_CONTROLLER 0x0d10 +#define PCI_CLASS_WIRELESS_WHCI 0x0d1010 + #define PCI_BASE_CLASS_INTELLIGENT 0x0e #define PCI_CLASS_INTELLIGENT_I2O 0x0e00 @@ -129,6 +133,9 @@ /* Vendors and devices. Sort key: vendor first, device next. */ +#define PCI_VENDOR_ID_TTTECH 0x0357 +#define PCI_DEVICE_ID_TTTECH_MC322 0x000a + #define PCI_VENDOR_ID_DYNALINK 0x0675 #define PCI_DEVICE_ID_DYNALINK_IS64PH 0x1702 @@ -468,8 +475,8 @@ #define PCI_DEVICE_ID_IBM_ICOM_DEV_ID_2 0x0219 #define PCI_DEVICE_ID_IBM_ICOM_V2_TWO_PORTS_RVX 0x021A #define PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM 0x0251 +#define PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM_PCIE 0x0361 #define PCI_DEVICE_ID_IBM_ICOM_FOUR_PORT_MODEL 0x252 -#define PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM_PCIE 0x0361 #define PCI_VENDOR_ID_UNISYS 0x1018 #define PCI_DEVICE_ID_UNISYS_DMA_DIRECTOR 0x001C @@ -487,7 +494,19 @@ #define PCI_VENDOR_ID_AMD 0x1022 #define PCI_DEVICE_ID_AMD_K8_NB 0x1100 +#define PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP 0x1101 +#define PCI_DEVICE_ID_AMD_K8_NB_MEMCTL 0x1102 #define PCI_DEVICE_ID_AMD_K8_NB_MISC 0x1103 +#define PCI_DEVICE_ID_AMD_10H_NB_HT 0x1200 +#define PCI_DEVICE_ID_AMD_10H_NB_MAP 0x1201 +#define PCI_DEVICE_ID_AMD_10H_NB_DRAM 0x1202 +#define PCI_DEVICE_ID_AMD_10H_NB_MISC 0x1203 +#define PCI_DEVICE_ID_AMD_10H_NB_LINK 0x1204 +#define PCI_DEVICE_ID_AMD_11H_NB_HT 0x1300 +#define PCI_DEVICE_ID_AMD_11H_NB_MAP 0x1301 +#define PCI_DEVICE_ID_AMD_11H_NB_DRAM 0x1302 +#define PCI_DEVICE_ID_AMD_11H_NB_MISC 0x1303 +#define PCI_DEVICE_ID_AMD_11H_NB_LINK 0x1304 #define PCI_DEVICE_ID_AMD_LANCE 0x2000 #define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001 #define PCI_DEVICE_ID_AMD_SCSI 0x2020 @@ -568,6 +587,7 @@ #define PCI_DEVICE_ID_MATROX_G200_PCI 0x0520 #define PCI_DEVICE_ID_MATROX_G200_AGP 0x0521 #define PCI_DEVICE_ID_MATROX_G400 0x0525 +#define PCI_DEVICE_ID_MATROX_G200EV_PCI 0x0530 #define PCI_DEVICE_ID_MATROX_G550 0x2527 #define PCI_DEVICE_ID_MATROX_VIA 0x4536 @@ -601,7 +621,6 @@ #define PCI_DEVICE_ID_NEC_CBUS_3 0x003b #define PCI_DEVICE_ID_NEC_NAPCCARD 0x003e #define PCI_DEVICE_ID_NEC_PCX2 0x0046 /* PowerVR */ -#define PCI_DEVICE_ID_NEC_NILE4 0x005a #define PCI_DEVICE_ID_NEC_VRC5476 0x009b #define PCI_DEVICE_ID_NEC_VRC4173 0x00a5 #define PCI_DEVICE_ID_NEC_VRC5477_AC97 0x00a6 @@ -660,6 +679,7 @@ #define PCI_DEVICE_ID_SI_965 0x0965 #define PCI_DEVICE_ID_SI_966 0x0966 #define PCI_DEVICE_ID_SI_968 0x0968 +#define PCI_DEVICE_ID_SI_1180 0x1180 #define PCI_DEVICE_ID_SI_5511 0x5511 #define PCI_DEVICE_ID_SI_5513 0x5513 #define PCI_DEVICE_ID_SI_5517 0x5517 @@ -707,7 +727,7 @@ #define PCI_DEVICE_ID_HP_CISSA 0x3220 #define PCI_DEVICE_ID_HP_CISSC 0x3230 #define PCI_DEVICE_ID_HP_CISSD 0x3238 -#define PCI_DEVICE_ID_HP_CISSE 0x323A +#define PCI_DEVICE_ID_HP_CISSE 0x323a #define PCI_DEVICE_ID_HP_ZX2_IOC 0x4031 #define PCI_VENDOR_ID_PCTECH 0x1042 @@ -731,7 +751,6 @@ #define PCI_DEVICE_ID_ELSA_MICROLINK 0x1000 #define PCI_DEVICE_ID_ELSA_QS3000 0x3000 - #define PCI_VENDOR_ID_BUSLOGIC 0x104B #define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140 #define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER 0x1040 @@ -740,10 +759,13 @@ #define PCI_VENDOR_ID_TI 0x104c #define PCI_DEVICE_ID_TI_TVP4020 0x3d07 #define PCI_DEVICE_ID_TI_4450 0x8011 +#define PCI_DEVICE_ID_TI_TSB43AB22 0x8023 #define PCI_DEVICE_ID_TI_XX21_XX11 0x8031 +#define PCI_DEVICE_ID_TI_XX21_XX11_FM 0x8033 #define PCI_DEVICE_ID_TI_XX21_XX11_SD 0x8034 #define PCI_DEVICE_ID_TI_X515 0x8036 #define PCI_DEVICE_ID_TI_XX12 0x8039 +#define PCI_DEVICE_ID_TI_XX12_FM 0x803b #define PCI_DEVICE_ID_TI_1130 0xac12 #define PCI_DEVICE_ID_TI_1031 0xac13 #define PCI_DEVICE_ID_TI_1131 0xac15 @@ -771,10 +793,10 @@ #define PCI_DEVICE_ID_TI_1510 0xac56 #define PCI_DEVICE_ID_TI_X620 0xac8d #define PCI_DEVICE_ID_TI_X420 0xac8e +#define PCI_DEVICE_ID_TI_XX20_FM 0xac8f #define PCI_VENDOR_ID_SONY 0x104d - /* Winbond have two vendor IDs! See 0x10ad as well */ #define PCI_VENDOR_ID_WINBOND2 0x1050 #define PCI_DEVICE_ID_WINBOND2_89C940F 0x5a5a @@ -812,12 +834,14 @@ #define PCI_DEVICE_ID_PROMISE_20276 0x5275 #define PCI_DEVICE_ID_PROMISE_20277 0x7275 - #define PCI_VENDOR_ID_UMC 0x1060 #define PCI_DEVICE_ID_UMC_UM8673F 0x0101 #define PCI_DEVICE_ID_UMC_UM8886BF 0x673a #define PCI_DEVICE_ID_UMC_UM8886A 0x886a +#define PCI_VENDOR_ID_PICOPOWER 0x1066 +#define PCI_DEVICE_ID_PICOPOWER_PT86C523 0x0002 +#define PCI_DEVICE_ID_PICOPOWER_PT86C523BBP 0x8002 #define PCI_VENDOR_ID_MYLEX 0x1069 #define PCI_DEVICE_ID_MYLEX_DAC960_P 0x0001 @@ -828,7 +852,6 @@ #define PCI_DEVICE_ID_MYLEX_DAC960_BA 0xBA56 #define PCI_DEVICE_ID_MYLEX_DAC960_GEM 0xB166 - #define PCI_VENDOR_ID_APPLE 0x106b #define PCI_DEVICE_ID_APPLE_BANDIT 0x0001 #define PCI_DEVICE_ID_APPLE_HYDRA 0x000e @@ -864,7 +887,6 @@ #define PCI_DEVICE_ID_YAMAHA_744 0x0010 #define PCI_DEVICE_ID_YAMAHA_754 0x0012 - #define PCI_VENDOR_ID_QLOGIC 0x1077 #define PCI_DEVICE_ID_QLOGIC_ISP10160 0x1016 #define PCI_DEVICE_ID_QLOGIC_ISP1020 0x1020 @@ -895,12 +917,9 @@ #define PCI_DEVICE_ID_CYRIX_5530_AUDIO 0x0103 #define PCI_DEVICE_ID_CYRIX_5530_VIDEO 0x0104 - - #define PCI_VENDOR_ID_CONTAQ 0x1080 #define PCI_DEVICE_ID_CONTAQ_82C693 0xc693 - #define PCI_VENDOR_ID_OLICOM 0x108d #define PCI_DEVICE_ID_OLICOM_OC2325 0x0012 #define PCI_DEVICE_ID_OLICOM_OC2183 0x0013 @@ -932,23 +951,19 @@ #define PCI_DEVICE_ID_SII_3112 0x3112 #define PCI_DEVICE_ID_SII_1210SA 0x0240 - #define PCI_VENDOR_ID_BROOKTREE 0x109e #define PCI_DEVICE_ID_BROOKTREE_878 0x0878 #define PCI_DEVICE_ID_BROOKTREE_879 0x0879 - #define PCI_VENDOR_ID_SGI 0x10a9 #define PCI_DEVICE_ID_SGI_IOC3 0x0003 +#define PCI_DEVICE_ID_SGI_LITHIUM 0x1002 #define PCI_DEVICE_ID_SGI_IOC4 0x100a -#define PCI_VENDOR_ID_SGI_LITHIUM 0x1002 - #define PCI_VENDOR_ID_WINBOND 0x10ad #define PCI_DEVICE_ID_WINBOND_82C105 0x0105 #define PCI_DEVICE_ID_WINBOND_83C553 0x0565 - #define PCI_VENDOR_ID_PLX 0x10b5 #define PCI_DEVICE_ID_PLX_R685 0x1030 #define PCI_DEVICE_ID_PLX_ROMULUS 0x106a @@ -959,6 +974,7 @@ #define PCI_DEVICE_ID_PLX_R753 0x1152 #define PCI_DEVICE_ID_PLX_OLITEC 0x1187 #define PCI_DEVICE_ID_PLX_PCI200SYN 0x3196 +#define PCI_DEVICE_ID_PLX_9030 0x9030 #define PCI_DEVICE_ID_PLX_9050 0x9050 #define PCI_DEVICE_ID_PLX_9080 0x9080 #define PCI_DEVICE_ID_PLX_GTEK_SERIAL2 0xa001 @@ -981,7 +997,6 @@ #define PCI_DEVICE_ID_3COM_3CR990SVR97 0x9909 #define PCI_DEVICE_ID_3COM_3CR990SVR 0x990a - #define PCI_VENDOR_ID_AL 0x10b9 #define PCI_DEVICE_ID_AL_M1533 0x1533 #define PCI_DEVICE_ID_AL_M1535 0x1535 @@ -1004,18 +1019,14 @@ #define PCI_DEVICE_ID_AL_M5451 0x5451 #define PCI_DEVICE_ID_AL_M7101 0x7101 - - #define PCI_VENDOR_ID_NEOMAGIC 0x10c8 #define PCI_DEVICE_ID_NEOMAGIC_NM256AV_AUDIO 0x8005 #define PCI_DEVICE_ID_NEOMAGIC_NM256ZX_AUDIO 0x8006 #define PCI_DEVICE_ID_NEOMAGIC_NM256XL_PLUS_AUDIO 0x8016 - #define PCI_VENDOR_ID_TCONRAD 0x10da #define PCI_DEVICE_ID_TCONRAD_TOKENRING 0x0508 - #define PCI_VENDOR_ID_NVIDIA 0x10de #define PCI_DEVICE_ID_NVIDIA_TNT 0x0020 #define PCI_DEVICE_ID_NVIDIA_TNT2 0x0028 @@ -1212,11 +1223,13 @@ #define PCI_DEVICE_ID_NVIDIA_NVENET_16 0x03E5 #define PCI_DEVICE_ID_NVIDIA_NVENET_17 0x03E6 #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA 0x03E7 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SMBUS 0x03EB #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE 0x03EC #define PCI_DEVICE_ID_NVIDIA_NVENET_18 0x03EE #define PCI_DEVICE_ID_NVIDIA_NVENET_19 0x03EF #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2 0x03F6 #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3 0x03F7 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_SMBUS 0x0446 #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE 0x0448 #define PCI_DEVICE_ID_NVIDIA_NVENET_20 0x0450 #define PCI_DEVICE_ID_NVIDIA_NVENET_21 0x0451 @@ -1226,17 +1239,26 @@ #define PCI_DEVICE_ID_NVIDIA_NVENET_25 0x054D #define PCI_DEVICE_ID_NVIDIA_NVENET_26 0x054E #define PCI_DEVICE_ID_NVIDIA_NVENET_27 0x054F +#define PCI_DEVICE_ID_NVIDIA_NVENET_28 0x07DC +#define PCI_DEVICE_ID_NVIDIA_NVENET_29 0x07DD +#define PCI_DEVICE_ID_NVIDIA_NVENET_30 0x07DE +#define PCI_DEVICE_ID_NVIDIA_NVENET_31 0x07DF #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE 0x0560 #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE 0x056C #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE 0x0759 +#define PCI_DEVICE_ID_NVIDIA_NVENET_32 0x0760 +#define PCI_DEVICE_ID_NVIDIA_NVENET_33 0x0761 +#define PCI_DEVICE_ID_NVIDIA_NVENET_34 0x0762 +#define PCI_DEVICE_ID_NVIDIA_NVENET_35 0x0763 +#define PCI_DEVICE_ID_NVIDIA_NVENET_36 0x0AB0 +#define PCI_DEVICE_ID_NVIDIA_NVENET_37 0x0AB1 +#define PCI_DEVICE_ID_NVIDIA_NVENET_38 0x0AB2 +#define PCI_DEVICE_ID_NVIDIA_NVENET_39 0x0AB3 #define PCI_VENDOR_ID_IMS 0x10e0 #define PCI_DEVICE_ID_IMS_TT128 0x9128 #define PCI_DEVICE_ID_IMS_TT3D 0x9135 - - - #define PCI_VENDOR_ID_INTERG 0x10ea #define PCI_DEVICE_ID_INTERG_1682 0x1682 #define PCI_DEVICE_ID_INTERG_2000 0x2000 @@ -1255,7 +1277,6 @@ #define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP 0x3fc5 #define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI 0x3fc6 - #define PCI_VENDOR_ID_INIT 0x1101 #define PCI_VENDOR_ID_CREATIVE 0x1102 /* duplicate: ECTIVA */ @@ -1285,13 +1306,17 @@ #define PCI_DEVICE_ID_VIA_3296_0 0x0296 #define PCI_DEVICE_ID_VIA_8363_0 0x0305 #define PCI_DEVICE_ID_VIA_P4M800CE 0x0314 +#define PCI_DEVICE_ID_VIA_P4M890 0x0327 +#define PCI_DEVICE_ID_VIA_VT3324 0x0324 +#define PCI_DEVICE_ID_VIA_VT3336 0x0336 #define PCI_DEVICE_ID_VIA_VT3351 0x0351 +#define PCI_DEVICE_ID_VIA_VT3364 0x0364 #define PCI_DEVICE_ID_VIA_8371_0 0x0391 +#define PCI_DEVICE_ID_VIA_6415 0x0415 #define PCI_DEVICE_ID_VIA_8501_0 0x0501 #define PCI_DEVICE_ID_VIA_82C561 0x0561 #define PCI_DEVICE_ID_VIA_82C586_1 0x0571 #define PCI_DEVICE_ID_VIA_82C576 0x0576 -#define PCI_DEVICE_ID_VIA_SATA_EIDE 0x0581 #define PCI_DEVICE_ID_VIA_82C586_0 0x0586 #define PCI_DEVICE_ID_VIA_82C596 0x0596 #define PCI_DEVICE_ID_VIA_82C597_0 0x0597 @@ -1333,22 +1358,27 @@ #define PCI_DEVICE_ID_VIA_8783_0 0x3208 #define PCI_DEVICE_ID_VIA_8237 0x3227 #define PCI_DEVICE_ID_VIA_8251 0x3287 +#define PCI_DEVICE_ID_VIA_8261 0x3402 #define PCI_DEVICE_ID_VIA_8237A 0x3337 #define PCI_DEVICE_ID_VIA_8237S 0x3372 +#define PCI_DEVICE_ID_VIA_SATA_EIDE 0x5324 #define PCI_DEVICE_ID_VIA_8231 0x8231 #define PCI_DEVICE_ID_VIA_8231_4 0x8235 #define PCI_DEVICE_ID_VIA_8365_1 0x8305 #define PCI_DEVICE_ID_VIA_CX700 0x8324 +#define PCI_DEVICE_ID_VIA_CX700_IDE 0x0581 #define PCI_DEVICE_ID_VIA_VX800 0x8353 +#define PCI_DEVICE_ID_VIA_VX855 0x8409 #define PCI_DEVICE_ID_VIA_8371_1 0x8391 #define PCI_DEVICE_ID_VIA_82C598_1 0x8598 #define PCI_DEVICE_ID_VIA_838X_1 0xB188 #define PCI_DEVICE_ID_VIA_83_87XX_1 0xB198 +#define PCI_DEVICE_ID_VIA_C409_IDE 0XC409 +#define PCI_DEVICE_ID_VIA_ANON 0xFFFF #define PCI_VENDOR_ID_SIEMENS 0x110A #define PCI_DEVICE_ID_SIEMENS_DSCC4 0x2102 - #define PCI_VENDOR_ID_VORTEX 0x1119 #define PCI_DEVICE_ID_VORTEX_GDT60x0 0x0000 #define PCI_DEVICE_ID_VORTEX_GDT6000B 0x0001 @@ -1374,8 +1404,8 @@ #define PCI_VENDOR_ID_EF 0x111a #define PCI_DEVICE_ID_EF_ATM_FPGA 0x0000 #define PCI_DEVICE_ID_EF_ATM_ASIC 0x0002 -#define PCI_VENDOR_ID_EF_ATM_LANAI2 0x0003 -#define PCI_VENDOR_ID_EF_ATM_LANAIHB 0x0005 +#define PCI_DEVICE_ID_EF_ATM_LANAI2 0x0003 +#define PCI_DEVICE_ID_EF_ATM_LANAIHB 0x0005 #define PCI_VENDOR_ID_IDT 0x111d #define PCI_DEVICE_ID_IDT_IDT77201 0x0001 @@ -1383,7 +1413,6 @@ #define PCI_VENDOR_ID_FORE 0x1127 #define PCI_DEVICE_ID_FORE_PCA200E 0x0300 - #define PCI_VENDOR_ID_PHILIPS 0x1131 #define PCI_DEVICE_ID_PHILIPS_SAA7146 0x7146 #define PCI_DEVICE_ID_PHILIPS_SAA9730 0x9730 @@ -1398,11 +1427,12 @@ #define PCI_DEVICE_ID_EICON_MAESTRAQ_U 0xe013 #define PCI_DEVICE_ID_EICON_MAESTRAP 0xe014 +#define PCI_VENDOR_ID_CISCO 0x1137 + #define PCI_VENDOR_ID_ZIATECH 0x1138 #define PCI_DEVICE_ID_ZIATECH_5550_HC 0x5550 - #define PCI_VENDOR_ID_SYSKONNECT 0x1148 #define PCI_DEVICE_ID_SYSKONNECT_TR 0x4200 #define PCI_DEVICE_ID_SYSKONNECT_GE 0x4300 @@ -1410,23 +1440,22 @@ #define PCI_DEVICE_ID_SYSKONNECT_9DXX 0x4400 #define PCI_DEVICE_ID_SYSKONNECT_9MXX 0x4500 - #define PCI_VENDOR_ID_DIGI 0x114f #define PCI_DEVICE_ID_DIGI_DF_M_IOM2_E 0x0070 #define PCI_DEVICE_ID_DIGI_DF_M_E 0x0071 #define PCI_DEVICE_ID_DIGI_DF_M_IOM2_A 0x0072 #define PCI_DEVICE_ID_DIGI_DF_M_A 0x0073 +#define PCI_DEVICE_ID_DIGI_NEO_8 0x00B1 #define PCI_DEVICE_ID_NEO_2DB9 0x00C8 #define PCI_DEVICE_ID_NEO_2DB9PRI 0x00C9 #define PCI_DEVICE_ID_NEO_2RJ45 0x00CA #define PCI_DEVICE_ID_NEO_2RJ45PRI 0x00CB - +#define PCIE_DEVICE_ID_NEO_4_IBM 0x00F4 #define PCI_VENDOR_ID_XIRCOM 0x115d #define PCI_DEVICE_ID_XIRCOM_RBM56G 0x0101 #define PCI_DEVICE_ID_XIRCOM_X3201_MDM 0x0103 - #define PCI_VENDOR_ID_SERVERWORKS 0x1166 #define PCI_DEVICE_ID_SERVERWORKS_HE 0x0008 #define PCI_DEVICE_ID_SERVERWORKS_LE 0x0009 @@ -1460,10 +1489,14 @@ #define PCI_VENDOR_ID_TOSHIBA_2 0x102f #define PCI_DEVICE_ID_TOSHIBA_TC35815CF 0x0030 +#define PCI_DEVICE_ID_TOSHIBA_TC35815_NWU 0x0031 +#define PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939 0x0032 +#define PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE 0x0105 #define PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC 0x0108 #define PCI_DEVICE_ID_TOSHIBA_SPIDER_NET 0x01b3 #define PCI_VENDOR_ID_ATTO 0x117c + #define PCI_VENDOR_ID_RICOH 0x1180 #define PCI_DEVICE_ID_RICOH_RL5C465 0x0465 #define PCI_DEVICE_ID_RICOH_RL5C466 0x0466 @@ -1471,6 +1504,8 @@ #define PCI_DEVICE_ID_RICOH_RL5C476 0x0476 #define PCI_DEVICE_ID_RICOH_RL5C478 0x0478 #define PCI_DEVICE_ID_RICOH_R5C822 0x0822 +#define PCI_DEVICE_ID_RICOH_R5C832 0x0832 +#define PCI_DEVICE_ID_RICOH_R5C843 0x0843 #define PCI_VENDOR_ID_DLINK 0x1186 #define PCI_DEVICE_ID_DLINK_DGE510T 0x4c00 @@ -1493,7 +1528,6 @@ #define PCI_DEVICE_ID_ZEITNET_1221 0x0001 #define PCI_DEVICE_ID_ZEITNET_1225 0x0002 - #define PCI_VENDOR_ID_FUJITSU_ME 0x119e #define PCI_DEVICE_ID_FUJITSU_FS155 0x0001 #define PCI_DEVICE_ID_FUJITSU_FS50 0x0003 @@ -1506,36 +1540,31 @@ #define PCI_DEVICE_ID_MARVELL_GT64260 0x6430 #define PCI_DEVICE_ID_MARVELL_MV64360 0x6460 #define PCI_DEVICE_ID_MARVELL_MV64460 0x6480 -#define PCI_DEVICE_ID_MARVELL_GT96100 0x9652 -#define PCI_DEVICE_ID_MARVELL_GT96100A 0x9653 - +#define PCI_DEVICE_ID_MARVELL_88ALP01_NAND 0x4100 +#define PCI_DEVICE_ID_MARVELL_88ALP01_SD 0x4101 +#define PCI_DEVICE_ID_MARVELL_88ALP01_CCIC 0x4102 #define PCI_VENDOR_ID_V3 0x11b0 #define PCI_DEVICE_ID_V3_V960 0x0001 #define PCI_DEVICE_ID_V3_V351 0x0002 - #define PCI_VENDOR_ID_ATT 0x11c1 #define PCI_DEVICE_ID_ATT_VENUS_MODEM 0x480 - #define PCI_VENDOR_ID_SPECIALIX 0x11cb #define PCI_DEVICE_ID_SPECIALIX_IO8 0x2000 #define PCI_DEVICE_ID_SPECIALIX_RIO 0x8000 #define PCI_SUBDEVICE_ID_SPECIALIX_SPEED4 0xa004 - #define PCI_VENDOR_ID_ANALOG_DEVICES 0x11d4 #define PCI_DEVICE_ID_AD1889JS 0x1889 - #define PCI_DEVICE_ID_SEGA_BBA 0x1234 #define PCI_VENDOR_ID_ZORAN 0x11de #define PCI_DEVICE_ID_ZORAN_36057 0x6057 #define PCI_DEVICE_ID_ZORAN_36120 0x6120 - #define PCI_VENDOR_ID_COMPEX 0x11f6 #define PCI_DEVICE_ID_COMPEX_ENET100VG4 0x0112 @@ -1594,8 +1623,6 @@ #define PCI_DEVICE_ID_3DFX_VOODOO3 0x0005 #define PCI_DEVICE_ID_3DFX_VOODOO5 0x0009 - - #define PCI_VENDOR_ID_AVM 0x1244 #define PCI_DEVICE_ID_AVM_B1 0x0700 #define PCI_DEVICE_ID_AVM_C4 0x0800 @@ -1604,7 +1631,6 @@ #define PCI_DEVICE_ID_AVM_C2 0x1100 #define PCI_DEVICE_ID_AVM_T1 0x1200 - #define PCI_VENDOR_ID_STALLION 0x124d /* Allied Telesyn */ @@ -1627,7 +1653,6 @@ #define PCI_VENDOR_ID_SATSAGEM 0x1267 #define PCI_DEVICE_ID_SATSAGEM_NICCY 0x1016 - #define PCI_VENDOR_ID_ENSONIQ 0x1274 #define PCI_DEVICE_ID_ENSONIQ_CT5880 0x5880 #define PCI_DEVICE_ID_ENSONIQ_ES1370 0x5000 @@ -1639,11 +1664,10 @@ #define PCI_VENDOR_ID_ROCKWELL 0x127A #define PCI_VENDOR_ID_ITE 0x1283 -#define PCI_DEVICE_ID_ITE_IT8172G 0x8172 -#define PCI_DEVICE_ID_ITE_IT8172G_AUDIO 0x0801 #define PCI_DEVICE_ID_ITE_8211 0x8211 #define PCI_DEVICE_ID_ITE_8212 0x8212 #define PCI_DEVICE_ID_ITE_8213 0x8213 +#define PCI_DEVICE_ID_ITE_8152 0x8152 #define PCI_DEVICE_ID_ITE_8872 0x8872 #define PCI_DEVICE_ID_ITE_IT8330G_0 0xe886 @@ -1652,7 +1676,6 @@ #define PCI_VENDOR_ID_ALTEON 0x12ae - #define PCI_SUBVENDOR_ID_CONNECT_TECH 0x12c4 #define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232 0x0001 #define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232 0x0002 @@ -1683,7 +1706,6 @@ #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485 0x0331 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485 0x0332 - #define PCI_VENDOR_ID_NVIDIA_SGS 0x12d2 #define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018 @@ -1704,6 +1726,8 @@ #define PCI_VENDOR_ID_ELECTRONICDESIGNGMBH 0x12f8 #define PCI_DEVICE_ID_LML_33R10 0x8a02 +#define PCI_VENDOR_ID_ESDGMBH 0x12fe +#define PCI_DEVICE_ID_ESDGMBH_CPCIASIO4 0x0111 #define PCI_VENDOR_ID_SIIG 0x131f #define PCI_SUBVENDOR_ID_SIIG 0x131f @@ -1748,20 +1772,28 @@ #define PCI_DEVICE_ID_SIIG_8S_20x_650 0x2081 #define PCI_DEVICE_ID_SIIG_8S_20x_850 0x2082 #define PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL 0x2050 +#define PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL 0x2530 #define PCI_VENDOR_ID_RADISYS 0x1331 +#define PCI_VENDOR_ID_MICRO_MEMORY 0x1332 +#define PCI_DEVICE_ID_MICRO_MEMORY_5415CN 0x5415 +#define PCI_DEVICE_ID_MICRO_MEMORY_5425CN 0x5425 +#define PCI_DEVICE_ID_MICRO_MEMORY_6155 0x6155 + #define PCI_VENDOR_ID_DOMEX 0x134a #define PCI_DEVICE_ID_DOMEX_DMX3191D 0x0001 #define PCI_VENDOR_ID_INTASHIELD 0x135a #define PCI_DEVICE_ID_INTASHIELD_IS200 0x0d80 +#define PCI_DEVICE_ID_INTASHIELD_IS400 0x0dc0 #define PCI_VENDOR_ID_QUATECH 0x135C #define PCI_DEVICE_ID_QUATECH_QSC100 0x0010 #define PCI_DEVICE_ID_QUATECH_DSC100 0x0020 #define PCI_DEVICE_ID_QUATECH_ESC100D 0x0050 #define PCI_DEVICE_ID_QUATECH_ESC100M 0x0060 +#define PCI_DEVICE_ID_QUATECH_SPPXP_100 0x0278 #define PCI_VENDOR_ID_SEALEVEL 0x135e #define PCI_DEVICE_ID_SEALEVEL_U530 0x7101 @@ -1770,6 +1802,7 @@ #define PCI_DEVICE_ID_SEALEVEL_UCOMM232 0x7202 #define PCI_DEVICE_ID_SEALEVEL_COMM4 0x7401 #define PCI_DEVICE_ID_SEALEVEL_COMM8 0x7801 +#define PCI_DEVICE_ID_SEALEVEL_7803 0x7803 #define PCI_DEVICE_ID_SEALEVEL_UCOMM8 0x7804 #define PCI_VENDOR_ID_HYPERCOPE 0x1365 @@ -1791,7 +1824,6 @@ #define PCI_DEVICE_ID_LMC_SSI 0x0005 #define PCI_DEVICE_ID_LMC_T1 0x0006 - #define PCI_VENDOR_ID_NETGEAR 0x1385 #define PCI_DEVICE_ID_NETGEAR_GA620 0x620a @@ -1808,17 +1840,29 @@ #define PCI_DEVICE_ID_MOXA_C104 0x1040 #define PCI_DEVICE_ID_MOXA_CP104U 0x1041 #define PCI_DEVICE_ID_MOXA_CP104JU 0x1042 +#define PCI_DEVICE_ID_MOXA_CP104EL 0x1043 #define PCI_DEVICE_ID_MOXA_CT114 0x1140 #define PCI_DEVICE_ID_MOXA_CP114 0x1141 #define PCI_DEVICE_ID_MOXA_CP118U 0x1180 +#define PCI_DEVICE_ID_MOXA_CP118EL 0x1181 #define PCI_DEVICE_ID_MOXA_CP132 0x1320 #define PCI_DEVICE_ID_MOXA_CP132U 0x1321 #define PCI_DEVICE_ID_MOXA_CP134U 0x1340 #define PCI_DEVICE_ID_MOXA_C168 0x1680 #define PCI_DEVICE_ID_MOXA_CP168U 0x1681 +#define PCI_DEVICE_ID_MOXA_CP168EL 0x1682 +#define PCI_DEVICE_ID_MOXA_CP204J 0x2040 +#define PCI_DEVICE_ID_MOXA_C218 0x2180 +#define PCI_DEVICE_ID_MOXA_C320 0x3200 #define PCI_VENDOR_ID_CCD 0x1397 +#define PCI_DEVICE_ID_CCD_HFC4S 0x08B4 +#define PCI_SUBDEVICE_ID_CCD_PMX2S 0x1234 +#define PCI_DEVICE_ID_CCD_HFC8S 0x16B8 #define PCI_DEVICE_ID_CCD_2BD0 0x2bd0 +#define PCI_DEVICE_ID_CCD_HFCE1 0x30B1 +#define PCI_SUBDEVICE_ID_CCD_SPD4S 0x3136 +#define PCI_SUBDEVICE_ID_CCD_SPDE1 0x3137 #define PCI_DEVICE_ID_CCD_B000 0xb000 #define PCI_DEVICE_ID_CCD_B006 0xb006 #define PCI_DEVICE_ID_CCD_B007 0xb007 @@ -1828,8 +1872,32 @@ #define PCI_DEVICE_ID_CCD_B00B 0xb00b #define PCI_DEVICE_ID_CCD_B00C 0xb00c #define PCI_DEVICE_ID_CCD_B100 0xb100 +#define PCI_SUBDEVICE_ID_CCD_IOB4ST 0xB520 +#define PCI_SUBDEVICE_ID_CCD_IOB8STR 0xB521 +#define PCI_SUBDEVICE_ID_CCD_IOB8ST 0xB522 +#define PCI_SUBDEVICE_ID_CCD_IOB1E1 0xB523 +#define PCI_SUBDEVICE_ID_CCD_SWYX4S 0xB540 +#define PCI_SUBDEVICE_ID_CCD_JH4S20 0xB550 +#define PCI_SUBDEVICE_ID_CCD_IOB8ST_1 0xB552 +#define PCI_SUBDEVICE_ID_CCD_BN4S 0xB560 +#define PCI_SUBDEVICE_ID_CCD_BN8S 0xB562 +#define PCI_SUBDEVICE_ID_CCD_BNE1 0xB563 +#define PCI_SUBDEVICE_ID_CCD_BNE1D 0xB564 +#define PCI_SUBDEVICE_ID_CCD_BNE1DP 0xB565 +#define PCI_SUBDEVICE_ID_CCD_BN2S 0xB566 +#define PCI_SUBDEVICE_ID_CCD_BN1SM 0xB567 +#define PCI_SUBDEVICE_ID_CCD_BN4SM 0xB568 +#define PCI_SUBDEVICE_ID_CCD_BN2SM 0xB569 +#define PCI_SUBDEVICE_ID_CCD_BNE1M 0xB56A +#define PCI_SUBDEVICE_ID_CCD_BN8SP 0xB56B +#define PCI_SUBDEVICE_ID_CCD_HFC4S 0xB620 +#define PCI_SUBDEVICE_ID_CCD_HFC8S 0xB622 #define PCI_DEVICE_ID_CCD_B700 0xb700 #define PCI_DEVICE_ID_CCD_B701 0xb701 +#define PCI_SUBDEVICE_ID_CCD_HFCE1 0xC523 +#define PCI_SUBDEVICE_ID_CCD_OV2S 0xE884 +#define PCI_SUBDEVICE_ID_CCD_OV4S 0xE888 +#define PCI_SUBDEVICE_ID_CCD_OV8S 0xE998 #define PCI_VENDOR_ID_EXAR 0x13a8 #define PCI_DEVICE_ID_EXAR_XR17C152 0x0152 @@ -1851,6 +1919,8 @@ #define PCI_VENDOR_ID_ABOCOM 0x13D1 #define PCI_DEVICE_ID_ABOCOM_2BD1 0x2BD1 +#define PCI_VENDOR_ID_SUNDANCE 0x13f0 + #define PCI_VENDOR_ID_CMEDIA 0x13f6 #define PCI_DEVICE_ID_CMEDIA_CM8338A 0x0100 #define PCI_DEVICE_ID_CMEDIA_CM8338B 0x0101 @@ -1882,10 +1952,21 @@ #define PCI_VENDOR_ID_OXSEMI 0x1415 #define PCI_DEVICE_ID_OXSEMI_12PCI840 0x8403 +#define PCI_DEVICE_ID_OXSEMI_PCIe840 0xC000 +#define PCI_DEVICE_ID_OXSEMI_PCIe840_G 0xC004 +#define PCI_DEVICE_ID_OXSEMI_PCIe952_0 0xC100 +#define PCI_DEVICE_ID_OXSEMI_PCIe952_0_G 0xC104 +#define PCI_DEVICE_ID_OXSEMI_PCIe952_1 0xC110 +#define PCI_DEVICE_ID_OXSEMI_PCIe952_1_G 0xC114 +#define PCI_DEVICE_ID_OXSEMI_PCIe952_1_U 0xC118 +#define PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU 0xC11C #define PCI_DEVICE_ID_OXSEMI_16PCI954 0x9501 #define PCI_DEVICE_ID_OXSEMI_16PCI95N 0x9511 #define PCI_DEVICE_ID_OXSEMI_16PCI954PP 0x9513 #define PCI_DEVICE_ID_OXSEMI_16PCI952 0x9521 +#define PCI_DEVICE_ID_OXSEMI_16PCI952PP 0x9523 + +#define PCI_VENDOR_ID_CHELSIO 0x1425 #define PCI_VENDOR_ID_SAMSUNG 0x144d @@ -1908,6 +1989,8 @@ #define PCI_DEVICE_ID_PANACOM_QUADMODEM 0x0400 #define PCI_DEVICE_ID_PANACOM_DUALMODEM 0x0402 +#define PCI_VENDOR_ID_SIPACKETS 0x14d9 +#define PCI_DEVICE_ID_SP1011 0x0010 #define PCI_VENDOR_ID_AFAVLAB 0x14db #define PCI_DEVICE_ID_AFAVLAB_P028 0x2180 @@ -1929,6 +2012,8 @@ #define PCI_DEVICE_ID_NX2_5708 0x164c #define PCI_DEVICE_ID_TIGON3_5702FE 0x164d #define PCI_DEVICE_ID_NX2_57710 0x164e +#define PCI_DEVICE_ID_NX2_57711 0x164f +#define PCI_DEVICE_ID_NX2_57711E 0x1650 #define PCI_DEVICE_ID_TIGON3_5705 0x1653 #define PCI_DEVICE_ID_TIGON3_5705_2 0x1654 #define PCI_DEVICE_ID_TIGON3_5720 0x1658 @@ -1961,6 +2046,7 @@ #define PCI_DEVICE_ID_TIGON3_5787M 0x1693 #define PCI_DEVICE_ID_TIGON3_5782 0x1696 #define PCI_DEVICE_ID_TIGON3_5784 0x1698 +#define PCI_DEVICE_ID_TIGON3_5785 0x1699 #define PCI_DEVICE_ID_TIGON3_5786 0x169a #define PCI_DEVICE_ID_TIGON3_5787 0x169b #define PCI_DEVICE_ID_TIGON3_5788 0x169c @@ -1987,7 +2073,13 @@ #define PCI_VENDOR_ID_TOPIC 0x151f #define PCI_DEVICE_ID_TOPIC_TP560 0x0000 +#define PCI_VENDOR_ID_MAINPINE 0x1522 +#define PCI_DEVICE_ID_MAINPINE_PBRIDGE 0x0100 #define PCI_VENDOR_ID_ENE 0x1524 +#define PCI_DEVICE_ID_ENE_CB712_SD 0x0550 +#define PCI_DEVICE_ID_ENE_CB712_SD_2 0x0551 +#define PCI_DEVICE_ID_ENE_CB714_SD 0x0750 +#define PCI_DEVICE_ID_ENE_CB714_SD_2 0x0751 #define PCI_DEVICE_ID_ENE_1211 0x1211 #define PCI_DEVICE_ID_ENE_1225 0x1225 #define PCI_DEVICE_ID_ENE_1410 0x1410 @@ -1997,8 +2089,9 @@ #define PCI_DEVICE_ID_ENE_720 0x1421 #define PCI_DEVICE_ID_ENE_722 0x1422 -#define PCI_VENDOR_ID_CHELSIO 0x1425 - +#define PCI_SUBVENDOR_ID_PERLE 0x155f +#define PCI_SUBDEVICE_ID_PCI_RAS4 0xf001 +#define PCI_SUBDEVICE_ID_PCI_RAS8 0xf010 #define PCI_VENDOR_ID_SYBA 0x1592 #define PCI_DEVICE_ID_SYBA_2P_EPP 0x0782 @@ -2018,8 +2111,27 @@ #define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c #define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274 -#define PCI_VENDOR_ID_PDC 0x15e9 +#define PCI_VENDOR_ID_QUICKNET 0x15e2 +#define PCI_DEVICE_ID_QUICKNET_XJ 0x0500 +/* + * ADDI-DATA GmbH communication cards + */ +#define PCI_VENDOR_ID_ADDIDATA_OLD 0x10E8 +#define PCI_VENDOR_ID_ADDIDATA 0x15B8 +#define PCI_DEVICE_ID_ADDIDATA_APCI7500 0x7000 +#define PCI_DEVICE_ID_ADDIDATA_APCI7420 0x7001 +#define PCI_DEVICE_ID_ADDIDATA_APCI7300 0x7002 +#define PCI_DEVICE_ID_ADDIDATA_APCI7800 0x818E +#define PCI_DEVICE_ID_ADDIDATA_APCI7500_2 0x7009 +#define PCI_DEVICE_ID_ADDIDATA_APCI7420_2 0x700A +#define PCI_DEVICE_ID_ADDIDATA_APCI7300_2 0x700B +#define PCI_DEVICE_ID_ADDIDATA_APCI7500_3 0x700C +#define PCI_DEVICE_ID_ADDIDATA_APCI7420_3 0x700D +#define PCI_DEVICE_ID_ADDIDATA_APCI7300_3 0x700E +#define PCI_DEVICE_ID_ADDIDATA_APCI7800_3 0x700F + +#define PCI_VENDOR_ID_PDC 0x15e9 #define PCI_VENDOR_ID_FARSITE 0x1619 #define PCI_DEVICE_ID_FARSITE_T2P 0x0400 @@ -2031,14 +2143,21 @@ #define PCI_DEVICE_ID_FARSITE_TE1C 0x1612 #define PCI_VENDOR_ID_ARIMA 0x161f + #define PCI_VENDOR_ID_BROCADE 0x1657 #define PCI_VENDOR_ID_SIBYTE 0x166d +#define PCI_DEVICE_ID_BCM1250_PCI 0x0001 #define PCI_DEVICE_ID_BCM1250_HT 0x0002 +#define PCI_VENDOR_ID_ATHEROS 0x168c + #define PCI_VENDOR_ID_NETCELL 0x169c #define PCI_DEVICE_ID_REVOLUTION 0x0044 +#define PCI_VENDOR_ID_CENATEK 0x16CA +#define PCI_DEVICE_ID_CENATEK_IDE 0x0001 + #define PCI_VENDOR_ID_VITESSE 0x1725 #define PCI_DEVICE_ID_VITESSE_VSC7174 0x7174 @@ -2051,6 +2170,19 @@ #define PCI_DEVICE_ID_ALTIMA_AC9100 0x03ea #define PCI_DEVICE_ID_ALTIMA_AC1003 0x03eb +#define PCI_VENDOR_ID_BELKIN 0x1799 +#define PCI_DEVICE_ID_BELKIN_F5D7010V7 0x701f + +#define PCI_VENDOR_ID_RDC 0x17f3 +#define PCI_DEVICE_ID_RDC_R6020 0x6020 +#define PCI_DEVICE_ID_RDC_R6030 0x6030 +#define PCI_DEVICE_ID_RDC_R6040 0x6040 +#define PCI_DEVICE_ID_RDC_R6060 0x6060 +#define PCI_DEVICE_ID_RDC_R6061 0x6061 +#define PCI_DEVICE_ID_RDC_D1010 0x1010 + +#define PCI_VENDOR_ID_LENOVO 0x17aa + #define PCI_VENDOR_ID_ARECA 0x17d3 #define PCI_DEVICE_ID_ARECA_1110 0x1110 #define PCI_DEVICE_ID_ARECA_1120 0x1120 @@ -2077,7 +2209,6 @@ #define PCI_DEVICE_ID_HERC_WIN 0x5732 #define PCI_DEVICE_ID_HERC_UNI 0x5832 - #define PCI_VENDOR_ID_SITECOM 0x182d #define PCI_DEVICE_ID_SITECOM_DC105V2 0x3069 @@ -2086,8 +2217,35 @@ #define PCI_VENDOR_ID_TDI 0x192E #define PCI_DEVICE_ID_TDI_EHCI 0x0101 +#define PCI_VENDOR_ID_FREESCALE 0x1957 +#define PCI_DEVICE_ID_MPC8548E 0x0012 +#define PCI_DEVICE_ID_MPC8548 0x0013 +#define PCI_DEVICE_ID_MPC8543E 0x0014 +#define PCI_DEVICE_ID_MPC8543 0x0015 +#define PCI_DEVICE_ID_MPC8547E 0x0018 +#define PCI_DEVICE_ID_MPC8545E 0x0019 +#define PCI_DEVICE_ID_MPC8545 0x001a +#define PCI_DEVICE_ID_MPC8568E 0x0020 +#define PCI_DEVICE_ID_MPC8568 0x0021 +#define PCI_DEVICE_ID_MPC8567E 0x0022 +#define PCI_DEVICE_ID_MPC8567 0x0023 +#define PCI_DEVICE_ID_MPC8533E 0x0030 +#define PCI_DEVICE_ID_MPC8533 0x0031 +#define PCI_DEVICE_ID_MPC8544E 0x0032 +#define PCI_DEVICE_ID_MPC8544 0x0033 +#define PCI_DEVICE_ID_MPC8572E 0x0040 +#define PCI_DEVICE_ID_MPC8572 0x0041 +#define PCI_DEVICE_ID_MPC8536E 0x0050 +#define PCI_DEVICE_ID_MPC8536 0x0051 +#define PCI_DEVICE_ID_MPC8641 0x7010 +#define PCI_DEVICE_ID_MPC8641D 0x7011 +#define PCI_DEVICE_ID_MPC8610 0x7018 + +#define PCI_VENDOR_ID_PASEMI 0x1959 + #define PCI_VENDOR_ID_ATTANSIC 0x1969 #define PCI_DEVICE_ID_ATTANSIC_L1 0x1048 +#define PCI_DEVICE_ID_ATTANSIC_L2 0x2048 #define PCI_VENDOR_ID_JMICRON 0x197B #define PCI_DEVICE_ID_JMICRON_JMB360 0x2360 @@ -2096,10 +2254,22 @@ #define PCI_DEVICE_ID_JMICRON_JMB365 0x2365 #define PCI_DEVICE_ID_JMICRON_JMB366 0x2366 #define PCI_DEVICE_ID_JMICRON_JMB368 0x2368 +#define PCI_DEVICE_ID_JMICRON_JMB38X_SD 0x2381 +#define PCI_DEVICE_ID_JMICRON_JMB38X_MMC 0x2382 +#define PCI_DEVICE_ID_JMICRON_JMB38X_MS 0x2383 + +#define PCI_VENDOR_ID_KORENIX 0x1982 +#define PCI_DEVICE_ID_KORENIX_JETCARDF0 0x1600 +#define PCI_DEVICE_ID_KORENIX_JETCARDF1 0x16ff #define PCI_VENDOR_ID_TEKRAM 0x1de1 #define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 +#define PCI_VENDOR_ID_TEHUTI 0x1fc9 +#define PCI_DEVICE_ID_TEHUTI_3009 0x3009 +#define PCI_DEVICE_ID_TEHUTI_3010 0x3010 +#define PCI_DEVICE_ID_TEHUTI_3014 0x3014 + #define PCI_VENDOR_ID_HINT 0x3388 #define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013 @@ -2107,12 +2277,19 @@ #define PCI_DEVICE_ID_3DLABS_PERMEDIA2 0x0007 #define PCI_DEVICE_ID_3DLABS_PERMEDIA2V 0x0009 +#define PCI_VENDOR_ID_NETXEN 0x4040 +#define PCI_DEVICE_ID_NX2031_10GXSR 0x0001 +#define PCI_DEVICE_ID_NX2031_10GCX4 0x0002 +#define PCI_DEVICE_ID_NX2031_4GCU 0x0003 +#define PCI_DEVICE_ID_NX2031_IMEZ 0x0004 +#define PCI_DEVICE_ID_NX2031_HMEZ 0x0005 +#define PCI_DEVICE_ID_NX2031_XG_MGMT 0x0024 +#define PCI_DEVICE_ID_NX2031_XG_MGMT2 0x0025 +#define PCI_DEVICE_ID_NX3031 0x0100 #define PCI_VENDOR_ID_AKS 0x416c #define PCI_DEVICE_ID_AKS_ALADDINCARD 0x0100 - - #define PCI_VENDOR_ID_S3 0x5333 #define PCI_DEVICE_ID_S3_TRIO 0x8811 #define PCI_DEVICE_ID_S3_868 0x8880 @@ -2124,7 +2301,6 @@ #define PCI_VENDOR_ID_DUNORD 0x5544 #define PCI_DEVICE_ID_DUNORD_I3000 0x0001 - #define PCI_VENDOR_ID_DCI 0x6666 #define PCI_DEVICE_ID_DCI_PCCOM4 0x0001 #define PCI_DEVICE_ID_DCI_PCCOM8 0x0002 @@ -2142,6 +2318,9 @@ #define PCI_DEVICE_ID_INTEL_82378 0x0484 #define PCI_DEVICE_ID_INTEL_I960 0x0960 #define PCI_DEVICE_ID_INTEL_I960RM 0x0962 +#define PCI_DEVICE_ID_INTEL_8257X_SOL 0x1062 +#define PCI_DEVICE_ID_INTEL_82573E_SOL 0x1085 +#define PCI_DEVICE_ID_INTEL_82573L_SOL 0x108F #define PCI_DEVICE_ID_INTEL_82815_MC 0x1130 #define PCI_DEVICE_ID_INTEL_82815_CGC 0x1132 #define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221 @@ -2202,6 +2381,7 @@ #define PCI_DEVICE_ID_INTEL_82801EB_5 0x24d5 #define PCI_DEVICE_ID_INTEL_82801EB_6 0x24d6 #define PCI_DEVICE_ID_INTEL_82801EB_11 0x24db +#define PCI_DEVICE_ID_INTEL_82801EB_12 0x24dc #define PCI_DEVICE_ID_INTEL_82801EB_13 0x24dd #define PCI_DEVICE_ID_INTEL_ESB_1 0x25a1 #define PCI_DEVICE_ID_INTEL_ESB_2 0x25a2 @@ -2222,12 +2402,14 @@ #define PCI_DEVICE_ID_INTEL_82915G_IG 0x2582 #define PCI_DEVICE_ID_INTEL_82915GM_HB 0x2590 #define PCI_DEVICE_ID_INTEL_82915GM_IG 0x2592 +#define PCI_DEVICE_ID_INTEL_5000_ERR 0x25F0 +#define PCI_DEVICE_ID_INTEL_5000_FBD0 0x25F5 +#define PCI_DEVICE_ID_INTEL_5000_FBD1 0x25F6 #define PCI_DEVICE_ID_INTEL_82945G_HB 0x2770 #define PCI_DEVICE_ID_INTEL_82945G_IG 0x2772 #define PCI_DEVICE_ID_INTEL_3000_HB 0x2778 #define PCI_DEVICE_ID_INTEL_82945GM_HB 0x27A0 #define PCI_DEVICE_ID_INTEL_82945GM_IG 0x27A2 -#define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE #define PCI_DEVICE_ID_INTEL_ICH6_0 0x2640 #define PCI_DEVICE_ID_INTEL_ICH6_1 0x2641 #define PCI_DEVICE_ID_INTEL_ICH6_2 0x2642 @@ -2242,6 +2424,7 @@ #define PCI_DEVICE_ID_INTEL_ICH7_0 0x27b8 #define PCI_DEVICE_ID_INTEL_ICH7_1 0x27b9 #define PCI_DEVICE_ID_INTEL_ICH7_30 0x27b0 +#define PCI_DEVICE_ID_INTEL_TGP_LPC 0x27bc #define PCI_DEVICE_ID_INTEL_ICH7_31 0x27bd #define PCI_DEVICE_ID_INTEL_ICH7_17 0x27da #define PCI_DEVICE_ID_INTEL_ICH7_19 0x27dd @@ -2255,13 +2438,23 @@ #define PCI_DEVICE_ID_INTEL_ICH8_5 0x283e #define PCI_DEVICE_ID_INTEL_ICH8_6 0x2850 #define PCI_DEVICE_ID_INTEL_ICH9_0 0x2910 -#define PCI_DEVICE_ID_INTEL_ICH9_1 0x2911 +#define PCI_DEVICE_ID_INTEL_ICH9_1 0x2917 #define PCI_DEVICE_ID_INTEL_ICH9_2 0x2912 #define PCI_DEVICE_ID_INTEL_ICH9_3 0x2913 #define PCI_DEVICE_ID_INTEL_ICH9_4 0x2914 -#define PCI_DEVICE_ID_INTEL_ICH9_5 0x2915 +#define PCI_DEVICE_ID_INTEL_ICH9_5 0x2919 #define PCI_DEVICE_ID_INTEL_ICH9_6 0x2930 +#define PCI_DEVICE_ID_INTEL_ICH9_7 0x2916 +#define PCI_DEVICE_ID_INTEL_ICH9_8 0x2918 #define PCI_DEVICE_ID_INTEL_82855PM_HB 0x3340 +#define PCI_DEVICE_ID_INTEL_IOAT_TBG4 0x3429 +#define PCI_DEVICE_ID_INTEL_IOAT_TBG5 0x342a +#define PCI_DEVICE_ID_INTEL_IOAT_TBG6 0x342b +#define PCI_DEVICE_ID_INTEL_IOAT_TBG7 0x342c +#define PCI_DEVICE_ID_INTEL_IOAT_TBG0 0x3430 +#define PCI_DEVICE_ID_INTEL_IOAT_TBG1 0x3431 +#define PCI_DEVICE_ID_INTEL_IOAT_TBG2 0x3432 +#define PCI_DEVICE_ID_INTEL_IOAT_TBG3 0x3433 #define PCI_DEVICE_ID_INTEL_82830_HB 0x3575 #define PCI_DEVICE_ID_INTEL_82830_CGC 0x3577 #define PCI_DEVICE_ID_INTEL_82855GM_HB 0x3580 @@ -2275,12 +2468,25 @@ #define PCI_DEVICE_ID_INTEL_MCH_PC 0x3599 #define PCI_DEVICE_ID_INTEL_MCH_PC1 0x359a #define PCI_DEVICE_ID_INTEL_E7525_MCH 0x359e +#define PCI_DEVICE_ID_INTEL_IOAT_CNB 0x360b +#define PCI_DEVICE_ID_INTEL_FBD_CNB 0x360c #define PCI_DEVICE_ID_INTEL_ICH10_0 0x3a14 #define PCI_DEVICE_ID_INTEL_ICH10_1 0x3a16 #define PCI_DEVICE_ID_INTEL_ICH10_2 0x3a18 #define PCI_DEVICE_ID_INTEL_ICH10_3 0x3a1a #define PCI_DEVICE_ID_INTEL_ICH10_4 0x3a30 #define PCI_DEVICE_ID_INTEL_ICH10_5 0x3a60 +#define PCI_DEVICE_ID_INTEL_PCH_LPC_MIN 0x3b00 +#define PCI_DEVICE_ID_INTEL_PCH_LPC_MAX 0x3b1f +#define PCI_DEVICE_ID_INTEL_PCH_SMBUS 0x3b30 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB 0x402f +#define PCI_DEVICE_ID_INTEL_5100_16 0x65f0 +#define PCI_DEVICE_ID_INTEL_5100_21 0x65f5 +#define PCI_DEVICE_ID_INTEL_5100_22 0x65f6 +#define PCI_DEVICE_ID_INTEL_5400_ERR 0x4030 +#define PCI_DEVICE_ID_INTEL_5400_FBD0 0x4035 +#define PCI_DEVICE_ID_INTEL_5400_FBD1 0x4036 +#define PCI_DEVICE_ID_INTEL_IOAT_SCNB 0x65ff #define PCI_DEVICE_ID_INTEL_TOLAPAI_0 0x5031 #define PCI_DEVICE_ID_INTEL_TOLAPAI_1 0x5032 #define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000 @@ -2311,6 +2517,8 @@ #define PCI_DEVICE_ID_INTEL_82443GX_0 0x71a0 #define PCI_DEVICE_ID_INTEL_82443GX_2 0x71a2 #define PCI_DEVICE_ID_INTEL_82372FB_1 0x7601 +#define PCI_DEVICE_ID_INTEL_SCH_LPC 0x8119 +#define PCI_DEVICE_ID_INTEL_SCH_IDE 0x811a #define PCI_DEVICE_ID_INTEL_82454GX 0x84c4 #define PCI_DEVICE_ID_INTEL_82450GX 0x84c5 #define PCI_DEVICE_ID_INTEL_82451NX 0x84ca @@ -2378,7 +2586,6 @@ #define PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN 0x0500 #define PCI_DEVICE_ID_ADAPTEC2_SCAMP 0x0503 - #define PCI_VENDOR_ID_HOLTEK 0x9412 #define PCI_DEVICE_ID_HOLTEK_6565 0x6565 @@ -2394,6 +2601,11 @@ #define PCI_DEVICE_ID_NETMOS_9845 0x9845 #define PCI_DEVICE_ID_NETMOS_9855 0x9855 +#define PCI_VENDOR_ID_3COM_2 0xa727 + +#define PCI_VENDOR_ID_DIGIUM 0xd161 +#define PCI_DEVICE_ID_DIGIUM_HFC4S 0xb410 + #define PCI_SUBVENDOR_ID_EXSYS 0xd84d #define PCI_SUBDEVICE_ID_EXSYS_4014 0x4014 #define PCI_SUBDEVICE_ID_EXSYS_4055 0x4055 @@ -2402,11 +2614,7 @@ #define PCI_DEVICE_ID_TIGERJET_300 0x0001 #define PCI_DEVICE_ID_TIGERJET_100 0x0002 -#define PCI_VENDOR_ID_TTTECH 0x0357 -#define PCI_DEVICE_ID_TTTECH_MC322 0x000A - #define PCI_VENDOR_ID_XILINX_RME 0xea60 #define PCI_DEVICE_ID_RME_DIGI32 0x9896 #define PCI_DEVICE_ID_RME_DIGI32_PRO 0x9897 #define PCI_DEVICE_ID_RME_DIGI32_8 0x9898 - diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h index 944075cb..fbe835b7 100644 --- a/include/linux/pci_regs.h +++ b/include/linux/pci_regs.h @@ -202,10 +202,15 @@ #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ #define PCI_CAP_ID_HT 0x08 /* HyperTransport */ -#define PCI_CAP_ID_VNDR 0x09 /* Vendor specific capability */ +#define PCI_CAP_ID_VNDR 0x09 /* Vendor specific */ +#define PCI_CAP_ID_DBG 0x0A /* Debug port */ +#define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */ #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ +#define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */ +#define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */ #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ +#define PCI_CAP_ID_AF 0x13 /* Advanced Features Capability */ #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ #define PCI_CAP_SIZEOF 4 @@ -227,6 +232,7 @@ #define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */ #define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */ #define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */ +#define PCI_PM_CAP_PME_SHIFT 11 /* Start of the PME Mask in PMC */ #define PCI_PM_CTRL 4 /* PM control and status register */ #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ #define PCI_PM_CTRL_NO_SOFT_RESET 0x0004 /* No reset for D3hot->D0 */ @@ -234,6 +240,11 @@ #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ +#define PCI_PM_CTRL_DATA_DSTATE_MASK 0x3 /* D0 - D3 */ +#define PCI_PM_CTRL_D0 0x0 +#define PCI_PM_CTRL_D1 0x1 +#define PCI_PM_CTRL_D2 0x2 +#define PCI_PM_CTRL_D3HOT 0x3 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ @@ -316,7 +327,20 @@ #define PCI_X_CMD 2 /* Modes & Features */ #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ +#define PCI_X_CMD_READ_512 0x0000 /* 512 byte maximum read byte count */ +#define PCI_X_CMD_READ_1K 0x0004 /* 1Kbyte maximum read byte count */ +#define PCI_X_CMD_READ_2K 0x0008 /* 2Kbyte maximum read byte count */ +#define PCI_X_CMD_READ_4K 0x000c /* 4Kbyte maximum read byte count */ #define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */ + /* Max # of outstanding split transactions */ +#define PCI_X_CMD_SPLIT_1 0x0000 /* Max 1 */ +#define PCI_X_CMD_SPLIT_2 0x0010 /* Max 2 */ +#define PCI_X_CMD_SPLIT_3 0x0020 /* Max 3 */ +#define PCI_X_CMD_SPLIT_4 0x0030 /* Max 4 */ +#define PCI_X_CMD_SPLIT_8 0x0040 /* Max 8 */ +#define PCI_X_CMD_SPLIT_12 0x0050 /* Max 12 */ +#define PCI_X_CMD_SPLIT_16 0x0060 /* Max 16 */ +#define PCI_X_CMD_SPLIT_32 0x0070 /* Max 32 */ #define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */ #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ #define PCI_X_STATUS 4 /* PCI-X capabilities */ @@ -356,8 +380,10 @@ #define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */ #define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */ #define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */ +#define PCI_EXP_DEVCAP_RBER 0x8000 /* Role-Based Error Reporting */ #define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */ #define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */ +#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ #define PCI_EXP_DEVCTL 8 /* Device Control */ #define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */ #define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */ @@ -370,6 +396,7 @@ #define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */ #define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */ #define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ +#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ #define PCI_EXP_DEVSTA 10 /* Device Status */ #define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */ #define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */ @@ -378,9 +405,17 @@ #define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */ #define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */ #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ +#define PCI_EXP_LNKCAP_ASPMS 0xc00 /* ASPM Support */ +#define PCI_EXP_LNKCAP_L0SEL 0x7000 /* L0s Exit Latency */ +#define PCI_EXP_LNKCAP_L1EL 0x38000 /* L1 Exit Latency */ +#define PCI_EXP_LNKCAP_CLKPM 0x40000 /* L1 Clock Power Management */ #define PCI_EXP_LNKCTL 16 /* Link Control */ +#define PCI_EXP_LNKCTL_RL 0x20 /* Retrain Link */ +#define PCI_EXP_LNKCTL_CCC 0x40 /* Common Clock COnfiguration */ #define PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */ #define PCI_EXP_LNKSTA 18 /* Link Status */ +#define PCI_EXP_LNKSTA_LT 0x800 /* Link Training */ +#define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ #define PCI_EXP_SLTCTL 24 /* Slot Control */ #define PCI_EXP_SLTSTA 26 /* Slot Status */ @@ -392,6 +427,10 @@ #define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */ #define PCI_EXP_RTCAP 30 /* Root Capabilities */ #define PCI_EXP_RTSTA 32 /* Root Status */ +#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ +#define PCI_EXP_DEVCAP2_ARI 0x20 /* Alternative Routing-ID */ +#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ +#define PCI_EXP_DEVCTL2_ARI 0x20 /* Alternative Routing-ID */ /* Extended Capabilities (PCI-X 2.0 and Express) */ #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) @@ -402,6 +441,7 @@ #define PCI_EXT_CAP_ID_VC 2 #define PCI_EXT_CAP_ID_DSN 3 #define PCI_EXT_CAP_ID_PWR 4 +#define PCI_EXT_CAP_ID_ARI 14 /* Advanced Error Reporting */ #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ @@ -509,5 +549,24 @@ #define HT_CAPTYPE_GEN3 0xD0 /* Generation 3 hypertransport configuration */ #define HT_CAPTYPE_PM 0xE0 /* Hypertransport powermanagement configuration */ +/* Alternative Routing-ID Interpretation */ +#define PCI_ARI_CAP 0x04 /* ARI Capability Register */ +#define PCI_ARI_CAP_MFVC 0x0001 /* MFVC Function Groups Capability */ +#define PCI_ARI_CAP_ACS 0x0002 /* ACS Function Groups Capability */ +#define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) /* Next Function Number */ +#define PCI_ARI_CTRL 0x06 /* ARI Control Register */ +#define PCI_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */ +#define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */ +#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */ + +/* Advanced Features Capability */ +#define PCI_AF_LENGTH 0x06 +#define PCI_AF_DEVCAP 0x03 /* Device capabilities offset */ +#define PCI_AF_CAP_TP 0x01 +#define PCI_AF_CAP_FLR 0x02 +#define PCI_AF_CTRL 0x04 /* Device CTRL offset */ +#define PCI_AF_CTRL_FLR 0x01 +#define PCI_AF_STA 0x05 /* Device STATUS offset */ +#define PCI_AF_STA_TP 0x01 #endif /* LINUX_PCI_REGS_H */