From: ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Wed, 14 Nov 2007 03:11:17 +0000 (+0000)
Subject: Introduce 4KEm configuration with fixed MMU mapping. Delete bogus INSN_DSP
X-Git-Tag: qemu-xen-4.2.0~10765
X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=3e4587d5d1b8ccb28de9be2fbab724dc1cc89359;p=qemu-xen.git

Introduce 4KEm configuration with fixed MMU mapping. Delete bogus INSN_DSP
flags.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3637 c046a42c-6fe2-441c-8c8c-71466251a162
---

diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 44aff7f37c..d54e3b6770 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -128,6 +128,23 @@ static mips_def_t mips_defs[] =
         .CP0_Status_rw_bitmask = 0x1278FF17,
         .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
     },
+    {
+        .name = "4KEm",
+        .CP0_PRid = 0x00019100,
+        /* Config1 implemented, MIPS32R2, fixed mapping MMU,
+           no virtual icache, uncached coherency. */
+        .CP0_Config0 = (1 << CP0C0_M) | (0x1 << CP0C0_AR) |
+                    (0x3 << CP0C0_MT) | (0x2 << CP0C0_K0),
+        .CP0_Config1 = MIPS_CONFIG1 |
+		    (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+		    (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
+        .CP0_Config2 = MIPS_CONFIG2,
+        .CP0_Config3 = MIPS_CONFIG3,
+        .SYNCI_Step = 32,
+        .CCRes = 2,
+        .CP0_Status_rw_bitmask = 0x1258FF17,
+        .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
+    },
     {
         .name = "24Kc",
         .CP0_PRid = 0x00019300,
@@ -141,7 +158,7 @@ static mips_def_t mips_defs[] =
         .CCRes = 2,
         /* No DSP implemented. */
         .CP0_Status_rw_bitmask = 0x1278FF1F,
-        .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
+        .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
     },
     {
         .name = "24Kf",
@@ -158,7 +175,7 @@ static mips_def_t mips_defs[] =
         .CP0_Status_rw_bitmask = 0x3678FF1F,
         .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
                     (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
-        .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
+        .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
     },
     {
         .name = "34Kf",