From: aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Fri, 5 Sep 2008 19:07:53 +0000 (+0000)
Subject: fix alpha cmovxx instruction
X-Git-Tag: stefano.display-merge-start~618
X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=29d26d20e5b4a9f28cdd9d072b407223e7b0e610;p=qemu-xen-4.3-testing.git

fix alpha cmovxx instruction

The CMOV instruction is defined by the alpha manual as:

CMOVxx Ra.rq,Rb.rq,Rc.wq !Operate format
CMOVxx Ra.rq,#b.ib,Rc.wq !Operate format

Operation:
IF TEST(Rav, Condition_based_on_Opcode) THEN
Rc ← Rbv

The current qemu behavior inverses Ra and Rb.  This is fixed by this
patch.

Signed-off-by: Tristan Gingold <gingold@adacore.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5171 c046a42c-6fe2-441c-8c8c-71466251a162
---

diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 8376c043e..847646f0d 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -390,15 +390,15 @@ static always_inline void gen_cmov (DisasContext *ctx,
                                     int islit, int8_t lit)
 {
     if (ra != 31)
-        tcg_gen_mov_i64(cpu_T[1], cpu_ir[ra]);
+        tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
     else
-        tcg_gen_movi_i64(cpu_T[1], 0);
+        tcg_gen_movi_i64(cpu_T[0], 0);
     if (islit)
-        tcg_gen_movi_i64(cpu_T[0], lit);
+        tcg_gen_movi_i64(cpu_T[1], lit);
     else if (rb != 31)
-        tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]);
+        tcg_gen_mov_i64(cpu_T[1], cpu_ir[rb]);
     else
-        tcg_gen_movi_i64(cpu_T[0], 0);
+        tcg_gen_movi_i64(cpu_T[1], 0);
     (*gen_test_op)();
     gen_op_cmov_ir(rc);
 }