From: Izhar Ameer Shaikh Date: Tue, 3 Dec 2019 02:40:40 +0000 (-0800) Subject: platform: versal: add EEMI layer support X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=2088cf5d600090ec0b832262aab8b981131d4dd8;p=people%2Fsstabellini%2Fxen-unstable.git%2F.git platform: versal: add EEMI layer support This patch adds a support for PM EEMI API mediate layer support. Mapping between device, clock and reset nodes and corresponding base addresses is derived from topology information. Similar to ZU+, certain device nodes do not allow any operations such as turning off ACPU cores, LPD etc. Since there are a few significant changes to the handling of PM commands for versal due to various reasons (node value representations, additions/removal of commands etc.), there is a separate handler for versal platform. Signed-off-by: Izhar Ameer Shaikh Signed-off-by: Stefano Stabellini --- diff --git a/xen/arch/arm/platforms/Makefile b/xen/arch/arm/platforms/Makefile index 0aeb8d17b4..d98d08f2f5 100644 --- a/xen/arch/arm/platforms/Makefile +++ b/xen/arch/arm/platforms/Makefile @@ -10,5 +10,6 @@ obj-$(CONFIG_ALL64_PLAT) += thunderx.o obj-$(CONFIG_ALL64_PLAT) += xgene-storm.o obj-$(CONFIG_ALL64_PLAT) += brcm-raspberry-pi.o obj-$(CONFIG_ALL64_PLAT) += xilinx-versal.o +obj-$(CONFIG_ALL64_PLAT) += xilinx-versal-eemi.o obj-$(CONFIG_MPSOC_PLATFORM) += xilinx-zynqmp.o obj-$(CONFIG_MPSOC_PLATFORM) += xilinx-zynqmp-eemi.o diff --git a/xen/arch/arm/platforms/xilinx-versal-eemi.c b/xen/arch/arm/platforms/xilinx-versal-eemi.c new file mode 100644 index 0000000000..8b3c55c1fe --- /dev/null +++ b/xen/arch/arm/platforms/xilinx-versal-eemi.c @@ -0,0 +1,591 @@ +/* + * xen/arch/arm/platforms/xilinx-versal-eemi.c + * + * Xilinx Versal EEMI API mediator. + * + * Copyright (c) 2019 Xilinx Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * Selected set of memory mapped definitions of device nodes. + */ +struct pm_access +{ + uint32_t addr; + bool hwdom_access; /* HW domain gets access regardless. */ +}; + +/* + * This table maps a node into a memory address. + * If a guest has access to the address, it has enough control + * over the node to grant it access to EEMI calls for that node. + */ +#define PM_NODE_IDX(Id) ((Id) & 0x3FFF) + +static const struct pm_access pm_node_access[] = { + [PM_NODE_IDX(PM_DEV_ACPU_0)] = { 0 }, + [PM_NODE_IDX(PM_DEV_ACPU_1)] = { 0 }, + [PM_NODE_IDX(PM_DEV_RPU0_0)] = { MM_DEV_RPU0_0 }, + [PM_NODE_IDX(PM_DEV_RPU0_1)] = { MM_DEV_RPU0_1 }, + + [PM_NODE_IDX(PM_DEV_OCM_0)] = { MM_DEV_OCM_0 }, + [PM_NODE_IDX(PM_DEV_OCM_1)] = { MM_DEV_OCM_1 }, + [PM_NODE_IDX(PM_DEV_OCM_2)] = { MM_DEV_OCM_2 }, + [PM_NODE_IDX(PM_DEV_OCM_3)] = { MM_DEV_OCM_3 }, + [PM_NODE_IDX(PM_DEV_TCM_0_A)] = { MM_DEV_TCM_0_A }, + [PM_NODE_IDX(PM_DEV_TCM_0_B)] = { MM_DEV_TCM_0_B }, + [PM_NODE_IDX(PM_DEV_TCM_1_A)] = { MM_DEV_TCM_1_A }, + [PM_NODE_IDX(PM_DEV_TCM_1_B)] = { MM_DEV_TCM_1_B }, + + [PM_NODE_IDX(PM_DEV_L2_BANK_0)] = { .hwdom_access = true }, + + /* Should Dom0 have access to this? */ + [PM_NODE_IDX(PM_DEV_DDR_0)] = { .hwdom_access = true }, + + [PM_NODE_IDX(PM_DEV_USB_0)] = { MM_DEV_USB_0 }, + [PM_NODE_IDX(PM_DEV_GEM_0)] = { MM_DEV_GEM_0 }, + [PM_NODE_IDX(PM_DEV_GEM_1)] = { MM_DEV_GEM_1 }, + [PM_NODE_IDX(PM_DEV_SPI_0)] = { MM_DEV_SPI_0 }, + [PM_NODE_IDX(PM_DEV_SPI_1)] = { MM_DEV_SPI_1 }, + [PM_NODE_IDX(PM_DEV_I2C_0)] = { MM_DEV_I2C_0 }, + [PM_NODE_IDX(PM_DEV_I2C_1)] = { MM_DEV_I2C_1 }, + [PM_NODE_IDX(PM_DEV_CAN_FD_0)] = { MM_DEV_CAN_FD_0 }, + [PM_NODE_IDX(PM_DEV_CAN_FD_1)] = { MM_DEV_CAN_FD_1 }, + [PM_NODE_IDX(PM_DEV_UART_0)] = { MM_DEV_UART_0 }, + [PM_NODE_IDX(PM_DEV_UART_1)] = { MM_DEV_UART_1 }, + [PM_NODE_IDX(PM_DEV_GPIO)] = { MM_DEV_GPIO }, + [PM_NODE_IDX(PM_DEV_TTC_0)] = { MM_DEV_TTC_0 }, + [PM_NODE_IDX(PM_DEV_TTC_1)] = { MM_DEV_TTC_1 }, + [PM_NODE_IDX(PM_DEV_TTC_2)] = { MM_DEV_TTC_2 }, + [PM_NODE_IDX(PM_DEV_TTC_3)] = { MM_DEV_TTC_3 }, + [PM_NODE_IDX(PM_DEV_SWDT_LPD)] = { MM_DEV_SWDT_LPD }, + [PM_NODE_IDX(PM_DEV_SWDT_FPD)] = { MM_DEV_SWDT_FPD }, + [PM_NODE_IDX(PM_DEV_OSPI)] = { MM_DEV_OSPI }, + [PM_NODE_IDX(PM_DEV_QSPI)] = { MM_DEV_QSPI }, + [PM_NODE_IDX(PM_DEV_GPIO_PMC)] = { MM_DEV_GPIO_PMC }, + [PM_NODE_IDX(PM_DEV_I2C_PMC)] = { MM_DEV_I2C_PMC }, + [PM_NODE_IDX(PM_DEV_SDIO_0)] = { MM_DEV_SDIO_0 }, + [PM_NODE_IDX(PM_DEV_SDIO_1)] = { MM_DEV_SDIO_1 }, + + [PM_NODE_IDX(PM_DEV_PL_0)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_DEV_PL_1)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_DEV_PL_2)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_DEV_PL_3)] = { .hwdom_access = true }, + + [PM_NODE_IDX(PM_DEV_RTC)] = { MM_DEV_RTC }, + [PM_NODE_IDX(PM_DEV_ADMA_0)] = { MM_DEV_ADMA_0 }, + [PM_NODE_IDX(PM_DEV_ADMA_1)] = { MM_DEV_ADMA_1 }, + [PM_NODE_IDX(PM_DEV_ADMA_2)] = { MM_DEV_ADMA_2 }, + [PM_NODE_IDX(PM_DEV_ADMA_3)] = { MM_DEV_ADMA_3 }, + [PM_NODE_IDX(PM_DEV_ADMA_4)] = { MM_DEV_ADMA_4 }, + [PM_NODE_IDX(PM_DEV_ADMA_5)] = { MM_DEV_ADMA_5 }, + [PM_NODE_IDX(PM_DEV_ADMA_6)] = { MM_DEV_ADMA_6 }, + [PM_NODE_IDX(PM_DEV_ADMA_7)] = { MM_DEV_ADMA_7 }, + + [PM_NODE_IDX(PM_DEV_IPI_0)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_DEV_IPI_1)] = { MM_DEV_IPI_1 }, + [PM_NODE_IDX(PM_DEV_IPI_2)] = { MM_DEV_IPI_2 }, + [PM_NODE_IDX(PM_DEV_IPI_3)] = { MM_DEV_IPI_3 }, + [PM_NODE_IDX(PM_DEV_IPI_4)] = { MM_DEV_IPI_4 }, + [PM_NODE_IDX(PM_DEV_IPI_5)] = { MM_DEV_IPI_5 }, + [PM_NODE_IDX(PM_DEV_IPI_6)] = { MM_DEV_IPI_6 }, + + /* Should Dom0 have access to this? */ + [PM_NODE_IDX(PM_DEV_DDRMC_0)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_DEV_DDRMC_1)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_DEV_DDRMC_2)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_DEV_DDRMC_3)] = { .hwdom_access = true }, + + [PM_NODE_IDX(PM_DEV_GT_0)] = { MM_DEV_GT_0 }, + [PM_NODE_IDX(PM_DEV_GT_1)] = { MM_DEV_GT_1 }, + [PM_NODE_IDX(PM_DEV_GT_2)] = { MM_DEV_GT_2 }, + [PM_NODE_IDX(PM_DEV_GT_3)] = { MM_DEV_GT_3 }, + [PM_NODE_IDX(PM_DEV_GT_4)] = { MM_DEV_GT_4 }, + [PM_NODE_IDX(PM_DEV_GT_5)] = { MM_DEV_GT_5 }, + [PM_NODE_IDX(PM_DEV_GT_6)] = { MM_DEV_GT_6 }, + [PM_NODE_IDX(PM_DEV_GT_7)] = { MM_DEV_GT_7 }, + [PM_NODE_IDX(PM_DEV_GT_8)] = { MM_DEV_GT_8 }, + [PM_NODE_IDX(PM_DEV_GT_9)] = { MM_DEV_GT_9 }, + + [PM_NODE_IDX(PM_DEV_GT_10)] = { MM_DEV_GT_10 }, + [PM_NODE_IDX(PM_DEV_EFUSE_CACHE)] = { MM_DEV_EFUSE_CACHE }, + [PM_NODE_IDX(PM_DEV_AMS_ROOT)] = { MM_DEV_AMS_ROOT }, +}; + +/* + * This table maps a reset node into its corresponding device node. + * + * Note: reset nodes must be in ascending order! + */ +static const struct pm_access pm_rst_access[] = { + [PM_NODE_IDX(PM_RST_PMC_POR)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_PMC)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_PS_POR)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_PL_POR)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_NOC_POR)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_FPD_POR)] = { .hwdom_access = true }, + + /* We don't allow anyone to turn on/off the ACPUs. */ + [PM_NODE_IDX(PM_RST_ACPU_0_POR)] = { 0 }, + [PM_NODE_IDX(PM_RST_ACPU_1_POR)] = { 0 }, + + [PM_NODE_IDX(PM_RST_OCM2_POR)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_PS_SRST)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_PL_SRST)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_NOC)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_NPI)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_SYS_RST_1)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_SYS_RST_2)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_SYS_RST_3)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_FPD)] = { .hwdom_access = true }, + + [PM_NODE_IDX(PM_RST_PL0)] = { PM_NODE_IDX(PM_DEV_PL_0) }, + [PM_NODE_IDX(PM_RST_PL1)] = { PM_NODE_IDX(PM_DEV_PL_1) }, + [PM_NODE_IDX(PM_RST_PL2)] = { PM_NODE_IDX(PM_DEV_PL_2) }, + [PM_NODE_IDX(PM_RST_PL3)] = { PM_NODE_IDX(PM_DEV_PL_3) }, + + [PM_NODE_IDX(PM_RST_APU)] = { 0 }, + [PM_NODE_IDX(PM_RST_ACPU_0)] = { 0 }, + [PM_NODE_IDX(PM_RST_ACPU_1)] = { 0 }, + [PM_NODE_IDX(PM_RST_ACPU_L2)] = { 0 }, + [PM_NODE_IDX(PM_RST_ACPU_GIC)] = { 0 }, + + [PM_NODE_IDX(PM_RST_RPU_ISLAND)] = { PM_NODE_IDX(PM_DEV_RPU0_0) }, + [PM_NODE_IDX(PM_RST_RPU_AMBA)] = { PM_NODE_IDX(PM_DEV_RPU0_0) }, + [PM_NODE_IDX(PM_RST_R5_0)] = { PM_NODE_IDX(PM_DEV_RPU0_0) }, + [PM_NODE_IDX(PM_RST_R5_1)] = { PM_NODE_IDX(PM_DEV_RPU0_1) }, + + [PM_NODE_IDX(PM_RST_SYSMON_PMC_SEQ_RST)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_SYSMON_PMC_CFG_RST)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_SYSMON_FPD_CFG_RST)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_SYSMON_FPD_SEQ_RST)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_SYSMON_LPD)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_PDMA_RST1)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_PDMA_RST0)] = { .hwdom_access = true }, + + /* ADMA Channel 0 grants access to pull the reset signal. */ + [PM_NODE_IDX(PM_RST_ADMA)] = { PM_NODE_IDX(PM_DEV_ADMA_0) }, + [PM_NODE_IDX(PM_RST_TIMESTAMP)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_OCM)] = { PM_NODE_IDX(PM_DEV_OCM_0) }, + [PM_NODE_IDX(PM_RST_OCM2_RST)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_IPI)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_SBI)] = { .hwdom_access = true }, + + /* No ops on LPD */ + [PM_NODE_IDX(PM_RST_LPD)] = { 0 }, + + [PM_NODE_IDX(PM_RST_QSPI)] = { PM_NODE_IDX(PM_DEV_QSPI) }, + [PM_NODE_IDX(PM_RST_OSPI)] = { PM_NODE_IDX(PM_DEV_OSPI) }, + [PM_NODE_IDX(PM_RST_SDIO_0)] = { PM_NODE_IDX(PM_DEV_SDIO_0) }, + [PM_NODE_IDX(PM_RST_SDIO_1)] = { PM_NODE_IDX(PM_DEV_SDIO_1) }, + [PM_NODE_IDX(PM_RST_I2C_PMC)] = { PM_NODE_IDX(PM_DEV_I2C_PMC) }, + [PM_NODE_IDX(PM_RST_GPIO_PMC)] = { PM_NODE_IDX(PM_DEV_GPIO_PMC) }, + [PM_NODE_IDX(PM_RST_GEM_0)] = { PM_NODE_IDX(PM_DEV_GEM_0) }, + [PM_NODE_IDX(PM_RST_GEM_1)] = { PM_NODE_IDX(PM_DEV_GEM_1) }, + + [PM_NODE_IDX(PM_RST_SPARE)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_USB_0)] = { PM_NODE_IDX(PM_DEV_USB_0) }, + + [PM_NODE_IDX(PM_RST_UART_0)] = { PM_NODE_IDX(PM_DEV_UART_0) }, + [PM_NODE_IDX(PM_RST_UART_1)] = { PM_NODE_IDX(PM_DEV_UART_1) }, + [PM_NODE_IDX(PM_RST_SPI_0)] = { PM_NODE_IDX(PM_DEV_SPI_0) }, + [PM_NODE_IDX(PM_RST_SPI_1)] = { PM_NODE_IDX(PM_DEV_SPI_1) }, + [PM_NODE_IDX(PM_RST_CAN_FD_0)] = { PM_NODE_IDX(PM_DEV_CAN_FD_0) }, + [PM_NODE_IDX(PM_RST_CAN_FD_1)] = { PM_NODE_IDX(PM_DEV_CAN_FD_1) }, + [PM_NODE_IDX(PM_RST_I2C_0)] = { PM_NODE_IDX(PM_DEV_I2C_0) }, + [PM_NODE_IDX(PM_RST_I2C_1)] = { PM_NODE_IDX(PM_DEV_I2C_1) }, + + [PM_NODE_IDX(PM_RST_GPIO_LPD)] = { PM_NODE_IDX(PM_DEV_GPIO) }, + + [PM_NODE_IDX(PM_RST_TTC_0)] = { PM_NODE_IDX(PM_DEV_TTC_0) }, + [PM_NODE_IDX(PM_RST_TTC_1)] = { PM_NODE_IDX(PM_DEV_TTC_1) }, + [PM_NODE_IDX(PM_RST_TTC_2)] = { PM_NODE_IDX(PM_DEV_TTC_2) }, + [PM_NODE_IDX(PM_RST_TTC_3)] = { PM_NODE_IDX(PM_DEV_TTC_3) }, + + [PM_NODE_IDX(PM_RST_SWDT_FPD)] = { PM_NODE_IDX(PM_DEV_SWDT_FPD) }, + [PM_NODE_IDX(PM_RST_SWDT_LPD)] = { PM_NODE_IDX(PM_DEV_SWDT_LPD) }, + + [PM_NODE_IDX(PM_RST_USB)] = { PM_DEV_USB_0 }, + [PM_NODE_IDX(PM_RST_DPC)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_PMCDBG)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_DBG_TRACE)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_DBG_FPD)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_DBG_TSTMP)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_RPU0_DBG)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_RPU1_DBG)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_HSDP)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_DBG_LPD)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_CPM_POR)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_CPM)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_CPMDBG)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_PCIE_CFG)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_PCIE_CORE0)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_PCIE_CORE1)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_PCIE_DMA)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_CMN)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_L2_0)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_L2_1)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_ADDR_REMAP)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_CPI0)] = { .hwdom_access = true }, + [PM_NODE_IDX(PM_RST_CPI1)] = { .hwdom_access = true }, +}; + +struct pm_clk2node +{ + uint32_t clk_idx; + uint32_t dev_idx; +}; + +/* + * This table maps a clk node into a device node. + */ +#define PM_CLK2NODE(clk, dev) { .clk_idx = clk, .dev_idx = dev } + +static const struct pm_clk2node pm_clk_node_map[] = { + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_SYSMON_REF), PM_NODE_IDX(PM_DEV_AMS_ROOT)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_TTC0), PM_NODE_IDX(PM_DEV_TTC_0)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_TTC1), PM_NODE_IDX(PM_DEV_TTC_1)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_TTC2), PM_NODE_IDX(PM_DEV_TTC_2)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_TTC3), PM_NODE_IDX(PM_DEV_TTC_3)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_GEM_TSU), PM_NODE_IDX(PM_DEV_GEM_0)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_GEM_TSU), PM_NODE_IDX(PM_DEV_GEM_1)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_GEM0_RX), PM_NODE_IDX(PM_DEV_GEM_0)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_GEM0_TX), PM_NODE_IDX(PM_DEV_GEM_0)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_GEM1_RX), PM_NODE_IDX(PM_DEV_GEM_1)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_GEM1_TX), PM_NODE_IDX(PM_DEV_GEM_1)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_QSPI_REF), PM_NODE_IDX(PM_DEV_QSPI)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_OSPI_REF), PM_NODE_IDX(PM_DEV_OSPI)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_SDIO0_REF), PM_NODE_IDX(PM_DEV_SDIO_0)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_SDIO1_REF), PM_NODE_IDX(PM_DEV_SDIO_1)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_I2C_REF), PM_NODE_IDX(PM_DEV_I2C_PMC)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_PMC_PL0_REF), PM_NODE_IDX(PM_DEV_PL_0)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_PMC_PL1_REF), PM_NODE_IDX(PM_DEV_PL_1)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_PMC_PL2_REF), PM_NODE_IDX(PM_DEV_PL_2)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_PMC_PL3_REF), PM_NODE_IDX(PM_DEV_PL_3)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_ACPU), PM_NODE_IDX(PM_DEV_ACPU_0)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_ACPU), PM_NODE_IDX(PM_DEV_ACPU_1)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_ADMA), PM_NODE_IDX(PM_DEV_ADMA_0)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_ADMA), PM_NODE_IDX(PM_DEV_ADMA_1)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_ADMA), PM_NODE_IDX(PM_DEV_ADMA_2)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_ADMA), PM_NODE_IDX(PM_DEV_ADMA_3)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_ADMA), PM_NODE_IDX(PM_DEV_ADMA_4)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_ADMA), PM_NODE_IDX(PM_DEV_ADMA_5)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_ADMA), PM_NODE_IDX(PM_DEV_ADMA_6)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_ADMA), PM_NODE_IDX(PM_DEV_ADMA_7)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_GEM0_REF), PM_NODE_IDX(PM_DEV_GEM_0)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_GEM1_REF), PM_NODE_IDX(PM_DEV_GEM_1)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_GEM_TSU_REF), PM_NODE_IDX(PM_DEV_GEM_0)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_GEM_TSU_REF), PM_NODE_IDX(PM_DEV_GEM_1)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_USB0_BUS_REF), PM_NODE_IDX(PM_DEV_USB_0)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_UART0_REF), PM_NODE_IDX(PM_DEV_UART_0)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_UART1_REF), PM_NODE_IDX(PM_DEV_UART_1)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_SPI0_REF), PM_NODE_IDX(PM_DEV_SPI_0)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_SPI1_REF), PM_NODE_IDX(PM_DEV_SPI_1)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_CAN0_REF), PM_NODE_IDX(PM_DEV_CAN_FD_0)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_CAN1_REF), PM_NODE_IDX(PM_DEV_CAN_FD_1)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_I2C0_REF), PM_NODE_IDX(PM_DEV_I2C_0)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_I2C1_REF), PM_NODE_IDX(PM_DEV_I2C_1)), + PM_CLK2NODE(PM_NODE_IDX(PM_CLK_USB3_DUAL_REF), PM_NODE_IDX(PM_DEV_USB_0)), +}; + +/* Last clock node index */ +#define PM_CLK_END_IDX PM_NODE_IDX(PM_CLK_MIO) + +#define PM_CLK_SBCL_MASK (0x3F << 20) /* Clock subclass mask */ +#define PM_CLK_SBCL_PLL (0x01 << 20) /* PLL subclass value */ + +static bool pm_check_access(const struct pm_access *acl, struct domain *d, u32 idx) +{ + unsigned long mfn; + + if ( acl[idx].hwdom_access && is_hardware_domain(d) ) + return true; + + mfn = paddr_to_pfn(acl[idx].addr); + if ( !mfn ) + return false; + + return iomem_access_permitted(d, mfn, mfn); +} + +/* Check if a domain has access to a node. */ +static bool domain_has_node_access(struct domain *d, u32 node) +{ + u32 nd_idx = PM_NODE_IDX(node); + + if ( nd_idx >= ARRAY_SIZE(pm_node_access) ) + return false; + + return pm_check_access(pm_node_access, d, nd_idx); +} + +/* Check if a domain has access to a reset line. */ +static bool domain_has_reset_access(struct domain *d, u32 rst) +{ + u32 rst_idx = PM_NODE_IDX(rst); + + if ( rst_idx >= ARRAY_SIZE(pm_rst_access) ) + return false; + + return pm_check_access(pm_rst_access, d, rst_idx); +} + +/* Check if a clock id is valid */ +static bool clock_id_is_valid(u32 clk_id) +{ + u32 clk_idx = PM_NODE_IDX(clk_id); + + if ( clk_idx > PM_CLK_END_IDX ) + return false; + + return true; +} + +/* Check if a clock id belongs to pll type */ +static bool clock_id_is_pll(u32 clk_id) +{ + if ( ( clk_id & PM_CLK_SBCL_MASK ) == PM_CLK_SBCL_PLL ) + return true; + + return false; +} + +/* + * Check if a domain has access to a clock control. + * Note: domain has access to clock control if it has access to all the nodes + * the are driven by the target clock. + */ +static bool domain_has_clock_access(struct domain *d, u32 clk_id) +{ + uint32_t i; + bool access = false; + clk_id = PM_NODE_IDX(clk_id); + + for ( i = 0; i < ARRAY_SIZE(pm_clk_node_map) && + pm_clk_node_map[i].clk_idx <= clk_id; i++ ) + { + if ( pm_clk_node_map[i].clk_idx == clk_id ) + { + if ( !domain_has_node_access(d, pm_clk_node_map[i].dev_idx) ) + return false; + + access = true; + } + } + + return access; +} + +bool versal_eemi(struct cpu_user_regs *regs) +{ + struct arm_smccc_res res; + uint32_t fid = get_user_reg(regs, 0); + uint32_t nodeid = get_user_reg(regs, 1); + unsigned int pm_fn = fid & 0xFFFF; + enum pm_ret_status ret; + + switch (pm_fn) + { + /* Mandatory SMC32 functions. */ + case ARM_SMCCC_CALL_COUNT_FID(SIP): + case ARM_SMCCC_CALL_UID_FID(SIP): + case ARM_SMCCC_REVISION_FID(SIP): + goto forward_to_fw; + /* + * We can't allow CPUs to suspend without Xen knowing about it. + * We accept but ignore the request and wait for the guest to issue + * a WFI which Xen will trap and act accordingly upon. + */ + case EEMI_FID(PM_SELF_SUSPEND): + ret = XST_PM_SUCCESS; + goto done; + + case EEMI_FID(PM_GET_NODE_STATUS): + /* API for PUs. */ + case EEMI_FID(PM_REQ_SUSPEND): + case EEMI_FID(PM_FORCE_POWERDOWN): + case EEMI_FID(PM_ABORT_SUSPEND): + case EEMI_FID(PM_REQ_WAKEUP): + case EEMI_FID(PM_SET_WAKEUP_SOURCE): + /* API for slaves. */ + case EEMI_FID(PM_REQ_NODE): + case EEMI_FID(PM_RELEASE_NODE): + case EEMI_FID(PM_SET_REQUIREMENT): + case EEMI_FID(PM_SET_MAX_LATENCY): + if ( !domain_has_node_access(current->domain, nodeid) ) { + printk("versal-pm: fn=%d No access to node %d\n", pm_fn, nodeid); + ret = XST_PM_NO_ACCESS; + goto done; + } + goto forward_to_fw; + + case EEMI_FID(PM_RESET_ASSERT): + case EEMI_FID(PM_RESET_GET_STATUS): + if ( !domain_has_reset_access(current->domain, nodeid) ) { + printk("versal-pm: fn=%d No access to reset %d\n", pm_fn, nodeid); + ret = XST_PM_NO_ACCESS; + goto done; + } + goto forward_to_fw; + + /* These calls are safe and always allowed. */ + case EEMI_FID(PM_GET_TRUSTZONE_VERSION): + case EEMI_FID(PM_GET_API_VERSION): + case EEMI_FID(PM_GET_CHIPID): + case EEMI_FID(PM_FEATURE_CHECK): + goto forward_to_fw; + + /* Mediated MMIO access. */ + case EEMI_FID(PM_MMIO_WRITE): + case EEMI_FID(PM_MMIO_READ): + /* TBD */ + ret = XST_PM_NOTSUPPORTED; + goto done; + + /* Exclusive to the hardware domain. */ + case EEMI_FID(PM_INIT): + case EEMI_FID(PM_SET_CONFIGURATION): + case EEMI_FID(PM_FPGA_LOAD): + case EEMI_FID(PM_FPGA_GET_STATUS): + case EEMI_FID(PM_SECURE_SHA): + case EEMI_FID(PM_SECURE_RSA): + case EEMI_FID(PM_PINCTRL_SET_FUNCTION): + case EEMI_FID(PM_PINCTRL_REQUEST): + case EEMI_FID(PM_PINCTRL_RELEASE): + case EEMI_FID(PM_PINCTRL_GET_FUNCTION): + case EEMI_FID(PM_PINCTRL_CONFIG_PARAM_GET): + case EEMI_FID(PM_PINCTRL_CONFIG_PARAM_SET): + case EEMI_FID(PM_IOCTL): + case EEMI_FID(PM_QUERY_DATA): + if ( !is_hardware_domain(current->domain) ) { + printk("eemi: fn=%d No access", pm_fn); + ret = XST_PM_NO_ACCESS; + goto done; + } + goto forward_to_fw; + + case EEMI_FID(PM_CLOCK_SETRATE): + case EEMI_FID(PM_CLOCK_GETRATE): + ret = XST_PM_NOTSUPPORTED; + goto done; + + case EEMI_FID(PM_CLOCK_GETSTATE): + case EEMI_FID(PM_CLOCK_GETDIVIDER): + case EEMI_FID(PM_CLOCK_GETPARENT): + if ( !clock_id_is_valid(nodeid) ) + { + gprintk(XENLOG_WARNING, "versal-pm: fn=0x%08x Invalid clock=0x%08x\n", + pm_fn, nodeid); + ret = XST_PM_INVALID_PARAM; + goto done; + } + else + goto forward_to_fw; + + case EEMI_FID(PM_CLOCK_ENABLE): + case EEMI_FID(PM_CLOCK_DISABLE): + case EEMI_FID(PM_CLOCK_SETDIVIDER): + case EEMI_FID(PM_CLOCK_SETPARENT): + if ( !clock_id_is_valid(nodeid) ) + { + gprintk(XENLOG_WARNING, "versal-pm: fn=0x%08x Invalid clock=0x%08x\n", + pm_fn, nodeid); + ret = XST_PM_INVALID_PARAM; + goto done; + } + /* + * Allow pll clock nodes to passthrough since there is no device binded to them + */ + if ( clock_id_is_pll(nodeid) ) + { + goto forward_to_fw; + } + if ( !domain_has_clock_access(current->domain, nodeid) ) + { + gprintk(XENLOG_WARNING, "versal-pm: fn=0x%08x No access to clock=0x%08x\n", + pm_fn, nodeid); + ret = XST_PM_NO_ACCESS; + goto done; + } + goto forward_to_fw; + + case EEMI_FID(PM_PLL_GET_PARAMETER): + case EEMI_FID(PM_PLL_GET_MODE): + goto forward_to_fw; + + case EEMI_FID(PM_PLL_SET_PARAMETER): + case EEMI_FID(PM_PLL_SET_MODE): + if ( !domain_has_node_access(current->domain, nodeid) ) + { + gprintk(XENLOG_WARNING, "versal-pm: fn=0x%08x No access to pll=0x%08x\n", + pm_fn, nodeid); + ret = XST_PM_NO_ACCESS; + goto done; + } + goto forward_to_fw; + + /* These calls are never allowed. */ + case EEMI_FID(PM_SYSTEM_SHUTDOWN): + ret = XST_PM_NO_ACCESS; + goto done; + + case IPI_MAILBOX_FID(IPI_MAILBOX_OPEN): + case IPI_MAILBOX_FID(IPI_MAILBOX_RELEASE): + case IPI_MAILBOX_FID(IPI_MAILBOX_STATUS_ENQUIRY): + case IPI_MAILBOX_FID(IPI_MAILBOX_NOTIFY): + case IPI_MAILBOX_FID(IPI_MAILBOX_ACK): + case IPI_MAILBOX_FID(IPI_MAILBOX_ENABLE_IRQ): + case IPI_MAILBOX_FID(IPI_MAILBOX_DISABLE_IRQ): + if ( !is_hardware_domain(current->domain) ) + { + gprintk(XENLOG_WARNING, "IPI mailbox: fn=%u No access", pm_fn); + ret = XST_PM_NO_ACCESS; + goto done; + } + goto forward_to_fw; + + default: + printk("versal-pm: Unhandled PM Call: %d\n", (u32)fid); + return false; + } + +forward_to_fw: + /* Re-encode pm args. */ + arm_smccc_1_1_smc(get_user_reg(regs, 0), + get_user_reg(regs, 1), + get_user_reg(regs, 2), + get_user_reg(regs, 3), + get_user_reg(regs, 4), + get_user_reg(regs, 5), + get_user_reg(regs, 6), + get_user_reg(regs, 7), + &res); + + set_user_reg(regs, 0, res.a0); + set_user_reg(regs, 1, res.a1); + set_user_reg(regs, 2, res.a2); + set_user_reg(regs, 3, res.a3); + return true; + +done: + set_user_reg(regs, 0, ret); + return true; +} diff --git a/xen/arch/arm/platforms/xilinx-versal.c b/xen/arch/arm/platforms/xilinx-versal.c index aae32531a3..54171451d4 100644 --- a/xen/arch/arm/platforms/xilinx-versal.c +++ b/xen/arch/arm/platforms/xilinx-versal.c @@ -17,7 +17,8 @@ */ #include -#include +#include +#include static const char * const versal_dt_compat[] __initconst = { @@ -27,8 +28,6 @@ static const char * const versal_dt_compat[] __initconst = static bool versal_smc(struct cpu_user_regs *regs) { - struct arm_smccc_res res; - if ( !cpus_have_const_cap(ARM_SMCCC_1_1) ) { printk_once(XENLOG_WARNING @@ -37,24 +36,7 @@ static bool versal_smc(struct cpu_user_regs *regs) return false; } - if ( !is_hardware_domain(current->domain) ) - return false; - - arm_smccc_1_1_smc(get_user_reg(regs, 0), - get_user_reg(regs, 1), - get_user_reg(regs, 2), - get_user_reg(regs, 3), - get_user_reg(regs, 4), - get_user_reg(regs, 5), - get_user_reg(regs, 6), - get_user_reg(regs, 7), - &res); - - set_user_reg(regs, 0, res.a0); - set_user_reg(regs, 1, res.a1); - set_user_reg(regs, 2, res.a2); - set_user_reg(regs, 3, res.a3); - return true; + return versal_eemi(regs); } PLATFORM_START(xilinx_versal, "Xilinx Versal") diff --git a/xen/include/asm-arm/platforms/xilinx-versal-eemi.h b/xen/include/asm-arm/platforms/xilinx-versal-eemi.h new file mode 100644 index 0000000000..2690550ccb --- /dev/null +++ b/xen/include/asm-arm/platforms/xilinx-versal-eemi.h @@ -0,0 +1,410 @@ +#ifndef __ASM_ARM_PLATFORMS_XILINX_VERSAL_EEMI_H +#define __ASM_ARM_PLATFORMS_XILINX_VERSAL_EEMI_H + +/* Main PM Mediator entry. */ +extern bool versal_eemi(struct cpu_user_regs *regs); + +/* Power Nodes */ +#define PM_POWER_PMC (0x4208001U) +#define PM_POWER_LPD (0x4210002U) +#define PM_POWER_FPD (0x420c003U) +#define PM_POWER_NOC (0x4214004U) +#define PM_POWER_ME (0x421c005U) +#define PM_POWER_PLD (0x4220006U) +#define PM_POWER_CPM (0x4218007U) +#define PM_POWER_PL_SYSMON (0x4208008U) +#define PM_POWER_RPU0_0 (0x4104009U) +#define PM_POWER_GEM0 (0x410400aU) +#define PM_POWER_GEM1 (0x410400bU) +#define PM_POWER_OCM_0 (0x410400cU) +#define PM_POWER_OCM_1 (0x410400dU) +#define PM_POWER_OCM_2 (0x410400eU) +#define PM_POWER_OCM_3 (0x410400fU) +#define PM_POWER_TCM_0_A (0x4104010U) +#define PM_POWER_TCM_0_B (0x4104011U) +#define PM_POWER_TCM_1_A (0x4104012U) +#define PM_POWER_TCM_1_B (0x4104013U) +#define PM_POWER_ACPU_0 (0x4104014U) +#define PM_POWER_ACPU_1 (0x4104015U) +#define PM_POWER_L2_BANK_0 (0x4104016U) + +/* Reset Nodes */ +#define PM_RST_PMC_POR (0xc30c001U) +#define PM_RST_PMC (0xc410002U) +#define PM_RST_PS_POR (0xc30c003U) +#define PM_RST_PL_POR (0xc30c004U) +#define PM_RST_NOC_POR (0xc30c005U) +#define PM_RST_FPD_POR (0xc30c006U) +#define PM_RST_ACPU_0_POR (0xc30c007U) +#define PM_RST_ACPU_1_POR (0xc30c008U) +#define PM_RST_OCM2_POR (0xc30c009U) +#define PM_RST_PS_SRST (0xc41000aU) +#define PM_RST_PL_SRST (0xc41000bU) +#define PM_RST_NOC (0xc41000cU) +#define PM_RST_NPI (0xc41000dU) +#define PM_RST_SYS_RST_1 (0xc41000eU) +#define PM_RST_SYS_RST_2 (0xc41000fU) +#define PM_RST_SYS_RST_3 (0xc410010U) +#define PM_RST_FPD (0xc410011U) +#define PM_RST_PL0 (0xc410012U) +#define PM_RST_PL1 (0xc410013U) +#define PM_RST_PL2 (0xc410014U) +#define PM_RST_PL3 (0xc410015U) +#define PM_RST_APU (0xc410016U) +#define PM_RST_ACPU_0 (0xc410017U) +#define PM_RST_ACPU_1 (0xc410018U) +#define PM_RST_ACPU_L2 (0xc410019U) +#define PM_RST_ACPU_GIC (0xc41001aU) +#define PM_RST_RPU_ISLAND (0xc41001bU) +#define PM_RST_RPU_AMBA (0xc41001cU) +#define PM_RST_R5_0 (0xc41001dU) +#define PM_RST_R5_1 (0xc41001eU) +#define PM_RST_SYSMON_PMC_SEQ_RST (0xc41001fU) +#define PM_RST_SYSMON_PMC_CFG_RST (0xc410020U) +#define PM_RST_SYSMON_FPD_CFG_RST (0xc410021U) +#define PM_RST_SYSMON_FPD_SEQ_RST (0xc410022U) +#define PM_RST_SYSMON_LPD (0xc410023U) +#define PM_RST_PDMA_RST1 (0xc410024U) +#define PM_RST_PDMA_RST0 (0xc410025U) +#define PM_RST_ADMA (0xc410026U) +#define PM_RST_TIMESTAMP (0xc410027U) +#define PM_RST_OCM (0xc410028U) +#define PM_RST_OCM2_RST (0xc410029U) +#define PM_RST_IPI (0xc41002aU) +#define PM_RST_SBI (0xc41002bU) +#define PM_RST_LPD (0xc41002cU) +#define PM_RST_QSPI (0xc10402dU) +#define PM_RST_OSPI (0xc10402eU) +#define PM_RST_SDIO_0 (0xc10402fU) +#define PM_RST_SDIO_1 (0xc104030U) +#define PM_RST_I2C_PMC (0xc104031U) +#define PM_RST_GPIO_PMC (0xc104032U) +#define PM_RST_GEM_0 (0xc104033U) +#define PM_RST_GEM_1 (0xc104034U) +#define PM_RST_SPARE (0xc104035U) +#define PM_RST_USB_0 (0xc104036U) +#define PM_RST_UART_0 (0xc104037U) +#define PM_RST_UART_1 (0xc104038U) +#define PM_RST_SPI_0 (0xc104039U) +#define PM_RST_SPI_1 (0xc10403aU) +#define PM_RST_CAN_FD_0 (0xc10403bU) +#define PM_RST_CAN_FD_1 (0xc10403cU) +#define PM_RST_I2C_0 (0xc10403dU) +#define PM_RST_I2C_1 (0xc10403eU) +#define PM_RST_GPIO_LPD (0xc10403fU) +#define PM_RST_TTC_0 (0xc104040U) +#define PM_RST_TTC_1 (0xc104041U) +#define PM_RST_TTC_2 (0xc104042U) +#define PM_RST_TTC_3 (0xc104043U) +#define PM_RST_SWDT_FPD (0xc104044U) +#define PM_RST_SWDT_LPD (0xc104045U) +#define PM_RST_USB (0xc104046U) +#define PM_RST_DPC (0xc208047U) +#define PM_RST_PMCDBG (0xc208048U) +#define PM_RST_DBG_TRACE (0xc208049U) +#define PM_RST_DBG_FPD (0xc20804aU) +#define PM_RST_DBG_TSTMP (0xc20804bU) +#define PM_RST_RPU0_DBG (0xc20804cU) +#define PM_RST_RPU1_DBG (0xc20804dU) +#define PM_RST_HSDP (0xc20804eU) +#define PM_RST_DBG_LPD (0xc20804fU) +#define PM_RST_CPM_POR (0xc30c050U) +#define PM_RST_CPM (0xc410051U) +#define PM_RST_CPMDBG (0xc208052U) +#define PM_RST_PCIE_CFG (0xc410053U) +#define PM_RST_PCIE_CORE0 (0xc410054U) +#define PM_RST_PCIE_CORE1 (0xc410055U) +#define PM_RST_PCIE_DMA (0xc410056U) +#define PM_RST_CMN (0xc410057U) +#define PM_RST_L2_0 (0xc410058U) +#define PM_RST_L2_1 (0xc410059U) +#define PM_RST_ADDR_REMAP (0xc41005aU) +#define PM_RST_CPI0 (0xc41005bU) +#define PM_RST_CPI1 (0xc41005cU) + +/* Clock nodes */ +#define PM_CLK_PMC_PLL (0x8104001U) +#define PM_CLK_APU_PLL (0x8104002U) +#define PM_CLK_RPU_PLL (0x8104003U) +#define PM_CLK_CPM_PLL (0x8104004U) +#define PM_CLK_NOC_PLL (0x8104005U) +#define PM_CLK_PMC_PRESRC (0x8208007U) +#define PM_CLK_PMC_POSTCLK (0x8208008U) +#define PM_CLK_PMC_PLL_OUT (0x8208009U) +#define PM_CLK_PPLL (0x820800aU) +#define PM_CLK_NOC_PRESRC (0x820800bU) +#define PM_CLK_NOC_POSTCLK (0x820800cU) +#define PM_CLK_NOC_PLL_OUT (0x820800dU) +#define PM_CLK_NPLL (0x820800eU) +#define PM_CLK_APU_PRESRC (0x820800fU) +#define PM_CLK_APU_POSTCLK (0x8208010U) +#define PM_CLK_APU_PLL_OUT (0x8208011U) +#define PM_CLK_APLL (0x8208012U) +#define PM_CLK_RPU_PRESRC (0x8208013U) +#define PM_CLK_RPU_POSTCLK (0x8208014U) +#define PM_CLK_RPU_PLL_OUT (0x8208015U) +#define PM_CLK_RPLL (0x8208016U) +#define PM_CLK_CPM_PRESRC (0x8208017U) +#define PM_CLK_CPM_POSTCLK (0x8208018U) +#define PM_CLK_CPM_PLL_OUT (0x8208019U) +#define PM_CLK_CPLL (0x820801aU) +#define PM_CLK_PPLL_TO_XPD (0x820801bU) +#define PM_CLK_NPLL_TO_XPD (0x820801cU) +#define PM_CLK_APLL_TO_XPD (0x820801dU) +#define PM_CLK_RPLL_TO_XPD (0x820801eU) +#define PM_CLK_EFUSE_REF (0x820801fU) +#define PM_CLK_SYSMON_REF (0x8208020U) +#define PM_CLK_IRO_SUSPEND_REF (0x8208021U) +#define PM_CLK_USB_SUSPEND (0x8208022U) +#define PM_CLK_SWITCH_TIMEOUT (0x8208023U) +#define PM_CLK_RCLK_PMC (0x8208024U) +#define PM_CLK_RCLK_LPD (0x8208025U) +#define PM_CLK_WDT (0x8208026U) +#define PM_CLK_TTC0 (0x8208027U) +#define PM_CLK_TTC1 (0x8208028U) +#define PM_CLK_TTC2 (0x8208029U) +#define PM_CLK_TTC3 (0x820802aU) +#define PM_CLK_GEM_TSU (0x820802bU) +#define PM_CLK_GEM_TSU_LB (0x820802cU) +#define PM_CLK_MUXED_IRO_DIV2 (0x820802dU) +#define PM_CLK_MUXED_IRO_DIV4 (0x820802eU) +#define PM_CLK_PSM_REF (0x820802fU) +#define PM_CLK_GEM0_RX (0x8208030U) +#define PM_CLK_GEM0_TX (0x8208031U) +#define PM_CLK_GEM1_RX (0x8208032U) +#define PM_CLK_GEM1_TX (0x8208033U) +#define PM_CLK_CPM_CORE_REF (0x8208034U) +#define PM_CLK_CPM_LSBUS_REF (0x8208035U) +#define PM_CLK_CPM_DBG_REF (0x8208036U) +#define PM_CLK_CPM_AUX0_REF (0x8208037U) +#define PM_CLK_CPM_AUX1_REF (0x8208038U) +#define PM_CLK_QSPI_REF (0x8208039U) +#define PM_CLK_OSPI_REF (0x820803aU) +#define PM_CLK_SDIO0_REF (0x820803bU) +#define PM_CLK_SDIO1_REF (0x820803cU) +#define PM_CLK_PMC_LSBUS_REF (0x820803dU) +#define PM_CLK_I2C_REF (0x820803eU) +#define PM_CLK_TEST_PATTERN_REF (0x820803fU) +#define PM_CLK_DFT_OSC_REF (0x8208040U) +#define PM_CLK_PMC_PL0_REF (0x8208041U) +#define PM_CLK_PMC_PL1_REF (0x8208042U) +#define PM_CLK_PMC_PL2_REF (0x8208043U) +#define PM_CLK_PMC_PL3_REF (0x8208044U) +#define PM_CLK_CFU_REF (0x8208045U) +#define PM_CLK_SPARE_REF (0x8208046U) +#define PM_CLK_NPI_REF (0x8208047U) +#define PM_CLK_HSM0_REF (0x8208048U) +#define PM_CLK_HSM1_REF (0x8208049U) +#define PM_CLK_SD_DLL_REF (0x820804aU) +#define PM_CLK_FPD_TOP_SWITCH (0x820804bU) +#define PM_CLK_FPD_LSBUS (0x820804cU) +#define PM_CLK_ACPU (0x820804dU) +#define PM_CLK_DBG_TRACE (0x820804eU) +#define PM_CLK_DBG_FPD (0x820804fU) +#define PM_CLK_LPD_TOP_SWITCH (0x8208050U) +#define PM_CLK_ADMA (0x8208051U) +#define PM_CLK_LPD_LSBUS (0x8208052U) +#define PM_CLK_CPU_R5 (0x8208053U) +#define PM_CLK_CPU_R5_CORE (0x8208054U) +#define PM_CLK_CPU_R5_OCM (0x8208055U) +#define PM_CLK_CPU_R5_OCM2 (0x8208056U) +#define PM_CLK_IOU_SWITCH (0x8208057U) +#define PM_CLK_GEM0_REF (0x8208058U) +#define PM_CLK_GEM1_REF (0x8208059U) +#define PM_CLK_GEM_TSU_REF (0x820805aU) +#define PM_CLK_USB0_BUS_REF (0x820805bU) +#define PM_CLK_UART0_REF (0x820805cU) +#define PM_CLK_UART1_REF (0x820805dU) +#define PM_CLK_SPI0_REF (0x820805eU) +#define PM_CLK_SPI1_REF (0x820805fU) +#define PM_CLK_CAN0_REF (0x8208060U) +#define PM_CLK_CAN1_REF (0x8208061U) +#define PM_CLK_I2C0_REF (0x8208062U) +#define PM_CLK_I2C1_REF (0x8208063U) +#define PM_CLK_DBG_LPD (0x8208064U) +#define PM_CLK_TIMESTAMP_REF (0x8208065U) +#define PM_CLK_DBG_TSTMP (0x8208066U) +#define PM_CLK_CPM_TOPSW_REF (0x8208067U) +#define PM_CLK_USB3_DUAL_REF (0x8208068U) +#define PM_CLK_REF_CLK (0x830c06aU) +#define PM_CLK_PL_ALT_REF_CLK (0x830c06bU) +#define PM_CLK_MUXED_IRO (0x830c06cU) +#define PM_CLK_PL_EXT (0x830c06dU) +#define PM_CLK_PL_LB (0x830c06eU) +#define PM_CLK_MIO_50_OR_51 (0x830c06fU) +#define PM_CLK_MIO_24_OR_25 (0x830c070U) +#define PM_CLK_EMIO (0x830c071U) +#define PM_CLK_MIO (0x830c072U) + +/* MIO nodes */ +#define PM_STMIC_LMIO_0 (0x14104001U) +#define PM_STMIC_LMIO_1 (0x14104002U) +#define PM_STMIC_LMIO_2 (0x14104003U) +#define PM_STMIC_LMIO_3 (0x14104004U) +#define PM_STMIC_LMIO_4 (0x14104005U) +#define PM_STMIC_LMIO_5 (0x14104006U) +#define PM_STMIC_LMIO_6 (0x14104007U) +#define PM_STMIC_LMIO_7 (0x14104008U) +#define PM_STMIC_LMIO_8 (0x14104009U) +#define PM_STMIC_LMIO_9 (0x1410400aU) +#define PM_STMIC_LMIO_10 (0x1410400bU) +#define PM_STMIC_LMIO_11 (0x1410400cU) +#define PM_STMIC_LMIO_12 (0x1410400dU) +#define PM_STMIC_LMIO_13 (0x1410400eU) +#define PM_STMIC_LMIO_14 (0x1410400fU) +#define PM_STMIC_LMIO_15 (0x14104010U) +#define PM_STMIC_LMIO_16 (0x14104011U) +#define PM_STMIC_LMIO_17 (0x14104012U) +#define PM_STMIC_LMIO_18 (0x14104013U) +#define PM_STMIC_LMIO_19 (0x14104014U) +#define PM_STMIC_LMIO_20 (0x14104015U) +#define PM_STMIC_LMIO_21 (0x14104016U) +#define PM_STMIC_LMIO_22 (0x14104017U) +#define PM_STMIC_LMIO_23 (0x14104018U) +#define PM_STMIC_LMIO_24 (0x14104019U) +#define PM_STMIC_LMIO_25 (0x1410401aU) +#define PM_STMIC_PMIO_0 (0x1410801bU) +#define PM_STMIC_PMIO_1 (0x1410801cU) +#define PM_STMIC_PMIO_2 (0x1410801dU) +#define PM_STMIC_PMIO_3 (0x1410801eU) +#define PM_STMIC_PMIO_4 (0x1410801fU) +#define PM_STMIC_PMIO_5 (0x14108020U) +#define PM_STMIC_PMIO_6 (0x14108021U) +#define PM_STMIC_PMIO_7 (0x14108022U) +#define PM_STMIC_PMIO_8 (0x14108023U) +#define PM_STMIC_PMIO_9 (0x14108024U) +#define PM_STMIC_PMIO_10 (0x14108025U) +#define PM_STMIC_PMIO_11 (0x14108026U) +#define PM_STMIC_PMIO_12 (0x14108027U) +#define PM_STMIC_PMIO_13 (0x14108028U) +#define PM_STMIC_PMIO_14 (0x14108029U) +#define PM_STMIC_PMIO_15 (0x1410802aU) +#define PM_STMIC_PMIO_16 (0x1410802bU) +#define PM_STMIC_PMIO_17 (0x1410802cU) +#define PM_STMIC_PMIO_18 (0x1410802dU) +#define PM_STMIC_PMIO_19 (0x1410802eU) +#define PM_STMIC_PMIO_20 (0x1410802fU) +#define PM_STMIC_PMIO_21 (0x14108030U) +#define PM_STMIC_PMIO_22 (0x14108031U) +#define PM_STMIC_PMIO_23 (0x14108032U) +#define PM_STMIC_PMIO_24 (0x14108033U) +#define PM_STMIC_PMIO_25 (0x14108034U) +#define PM_STMIC_PMIO_26 (0x14108035U) +#define PM_STMIC_PMIO_27 (0x14108036U) +#define PM_STMIC_PMIO_28 (0x14108037U) +#define PM_STMIC_PMIO_29 (0x14108038U) +#define PM_STMIC_PMIO_30 (0x14108039U) +#define PM_STMIC_PMIO_31 (0x1410803aU) +#define PM_STMIC_PMIO_32 (0x1410803bU) +#define PM_STMIC_PMIO_33 (0x1410803cU) +#define PM_STMIC_PMIO_34 (0x1410803dU) +#define PM_STMIC_PMIO_35 (0x1410803eU) +#define PM_STMIC_PMIO_36 (0x1410803fU) +#define PM_STMIC_PMIO_37 (0x14108040U) +#define PM_STMIC_PMIO_38 (0x14108041U) +#define PM_STMIC_PMIO_39 (0x14108042U) +#define PM_STMIC_PMIO_40 (0x14108043U) +#define PM_STMIC_PMIO_41 (0x14108044U) +#define PM_STMIC_PMIO_42 (0x14108045U) +#define PM_STMIC_PMIO_43 (0x14108046U) +#define PM_STMIC_PMIO_44 (0x14108047U) +#define PM_STMIC_PMIO_45 (0x14108048U) +#define PM_STMIC_PMIO_46 (0x14108049U) +#define PM_STMIC_PMIO_47 (0x1410804aU) +#define PM_STMIC_PMIO_48 (0x1410804bU) +#define PM_STMIC_PMIO_49 (0x1410804cU) +#define PM_STMIC_PMIO_50 (0x1410804dU) +#define PM_STMIC_PMIO_51 (0x1410804eU) + +/* Device Nodes */ +#define PM_DEV_PMC_PROC (0x18104001U) +#define PM_DEV_PSM_PROC (0x18108002U) +#define PM_DEV_ACPU_0 (0x1810c003U) +#define PM_DEV_ACPU_1 (0x1810c004U) +#define PM_DEV_RPU0_0 (0x18110005U) +#define PM_DEV_RPU0_1 (0x18110006U) +#define PM_DEV_OCM_0 (0x18314007U) +#define PM_DEV_OCM_1 (0x18314008U) +#define PM_DEV_OCM_2 (0x18314009U) +#define PM_DEV_OCM_3 (0x1831400aU) +#define PM_DEV_TCM_0_A (0x1831800bU) +#define PM_DEV_TCM_0_B (0x1831800cU) +#define PM_DEV_TCM_1_A (0x1831800dU) +#define PM_DEV_TCM_1_B (0x1831800eU) +#define PM_DEV_L2_BANK_0 (0x1831c00fU) +#define PM_DEV_DDR_0 (0x18320010U) +#define PM_DEV_USB_0 (0x18224018U) +#define PM_DEV_GEM_0 (0x18224019U) +#define PM_DEV_GEM_1 (0x1822401aU) +#define PM_DEV_SPI_0 (0x1822401bU) +#define PM_DEV_SPI_1 (0x1822401cU) +#define PM_DEV_I2C_0 (0x1822401dU) +#define PM_DEV_I2C_1 (0x1822401eU) +#define PM_DEV_CAN_FD_0 (0x1822401fU) +#define PM_DEV_CAN_FD_1 (0x18224020U) +#define PM_DEV_UART_0 (0x18224021U) +#define PM_DEV_UART_1 (0x18224022U) +#define PM_DEV_GPIO (0x18224023U) +#define PM_DEV_TTC_0 (0x18224024U) +#define PM_DEV_TTC_1 (0x18224025U) +#define PM_DEV_TTC_2 (0x18224026U) +#define PM_DEV_TTC_3 (0x18224027U) +#define PM_DEV_SWDT_LPD (0x18224028U) +#define PM_DEV_SWDT_FPD (0x18224029U) +#define PM_DEV_OSPI (0x1822402aU) +#define PM_DEV_QSPI (0x1822402bU) +#define PM_DEV_GPIO_PMC (0x1822402cU) +#define PM_DEV_I2C_PMC (0x1822402dU) +#define PM_DEV_SDIO_0 (0x1822402eU) +#define PM_DEV_SDIO_1 (0x1822402fU) +#define PM_DEV_PL_0 (0x18224030U) +#define PM_DEV_PL_1 (0x18224031U) +#define PM_DEV_PL_2 (0x18224032U) +#define PM_DEV_PL_3 (0x18224033U) +#define PM_DEV_RTC (0x18224034U) +#define PM_DEV_ADMA_0 (0x18224035U) +#define PM_DEV_ADMA_1 (0x18224036U) +#define PM_DEV_ADMA_2 (0x18224037U) +#define PM_DEV_ADMA_3 (0x18224038U) +#define PM_DEV_ADMA_4 (0x18224039U) +#define PM_DEV_ADMA_5 (0x1822403aU) +#define PM_DEV_ADMA_6 (0x1822403bU) +#define PM_DEV_ADMA_7 (0x1822403cU) +#define PM_DEV_IPI_0 (0x1822403dU) +#define PM_DEV_IPI_1 (0x1822403eU) +#define PM_DEV_IPI_2 (0x1822403fU) +#define PM_DEV_IPI_3 (0x18224040U) +#define PM_DEV_IPI_4 (0x18224041U) +#define PM_DEV_IPI_5 (0x18224042U) +#define PM_DEV_IPI_6 (0x18224043U) +#define PM_DEV_DDRMC_0 (0x18520045U) +#define PM_DEV_DDRMC_1 (0x18520046U) +#define PM_DEV_DDRMC_2 (0x18520047U) +#define PM_DEV_DDRMC_3 (0x18520048U) +#define PM_DEV_GT_0 (0x1862c049U) +#define PM_DEV_GT_1 (0x1862c04aU) +#define PM_DEV_GT_2 (0x1862c04bU) +#define PM_DEV_GT_3 (0x1862c04cU) +#define PM_DEV_GT_4 (0x1862c04dU) +#define PM_DEV_GT_5 (0x1862c04eU) +#define PM_DEV_GT_6 (0x1862c04fU) +#define PM_DEV_GT_7 (0x1862c050U) +#define PM_DEV_GT_8 (0x1862c051U) +#define PM_DEV_GT_9 (0x1862c052U) +#define PM_DEV_GT_10 (0x1862c053U) +#define PM_DEV_EFUSE_CACHE (0x18330054U) +#define PM_DEV_AMS_ROOT (0x18224055U) + +/* Subsystem Nodes */ +#define PM_SUBSYS_DEFAULT (0x1c000000U) +#define PM_SUBSYS_PMC (0x1c000001U) +#define PM_SUBSYS_PSM (0x1c000002U) +#define PM_SUBSYS_APU (0x1c000003U) +#define PM_SUBSYS_RPU0_LOCK (0x1c000004U) +#define PM_SUBSYS_RPU0_0 (0x1c000005U) +#define PM_SUBSYS_RPU0_1 (0x1c000006U) +#define PM_SUBSYS_DDR0 (0x1c000007U) +#define PM_SUBSYS_ME (0x1c000008U) +#define PM_SUBSYS_PL (0x1c000009U) + +#endif /* __ASM_ARM_PLATFORMS_XILINX_VERSAL_EEMI_H */ diff --git a/xen/include/asm-arm/platforms/xilinx-versal-mm.h b/xen/include/asm-arm/platforms/xilinx-versal-mm.h new file mode 100644 index 0000000000..f06b2fb08b --- /dev/null +++ b/xen/include/asm-arm/platforms/xilinx-versal-mm.h @@ -0,0 +1,83 @@ +#ifndef __ASM_ARM_PLATFORMS_XILINX_VERSAL_MM_H +#define __ASM_ARM_PLATFORMS_XILINX_VERSAL_MM_H + +/* + * Selected set of memory mapped definitions of device nodes. + */ +#define MM_DEV_ACPU_0 (0xfd5c0000U) +#define MM_DEV_ACPU_1 (0xfd5c0000U) +#define MM_DEV_RPU0_0 (0xff9a0000U) +#define MM_DEV_RPU0_1 (0xff9a0000U) +#define MM_DEV_OCM_0 (0xff960000U) +#define MM_DEV_OCM_1 (0xff960000U) +#define MM_DEV_OCM_2 (0xff960000U) +#define MM_DEV_OCM_3 (0xff960000U) +#define MM_DEV_TCM_0_A (0xffe00000U) +#define MM_DEV_TCM_0_B (0xffe20000U) +#define MM_DEV_TCM_1_A (0xffe90000U) +#define MM_DEV_TCM_1_B (0xffeb0000U) +#define MM_DEV_L2_BANK_0 (0U) +#define MM_DEV_DDR_0 (0U) +#define MM_DEV_USB_0 (0xff9d0000U) +#define MM_DEV_GEM_0 (0xff0c0000U) +#define MM_DEV_GEM_1 (0xff0d0000U) +#define MM_DEV_SPI_0 (0xff040000U) +#define MM_DEV_SPI_1 (0xff050000U) +#define MM_DEV_I2C_0 (0xff020000U) +#define MM_DEV_I2C_1 (0xff030000U) +#define MM_DEV_CAN_FD_0 (0xff060000U) +#define MM_DEV_CAN_FD_1 (0xff070000U) +#define MM_DEV_UART_0 (0xff000000U) +#define MM_DEV_UART_1 (0xff010000U) +#define MM_DEV_GPIO (0xff0b0000U) +#define MM_DEV_TTC_0 (0xff0e0000U) +#define MM_DEV_TTC_1 (0xff0f0000U) +#define MM_DEV_TTC_2 (0xff100000U) +#define MM_DEV_TTC_3 (0xff110000U) +#define MM_DEV_SWDT_LPD (0xff120000U) +#define MM_DEV_SWDT_FPD (0xfd4d0000U) +#define MM_DEV_OSPI (0xf1010000U) +#define MM_DEV_QSPI (0xf1030000U) +#define MM_DEV_GPIO_PMC (0xf1020000U) +#define MM_DEV_I2C_PMC (0xf1000000U) +#define MM_DEV_SDIO_0 (0xf1040000U) +#define MM_DEV_SDIO_1 (0xf1050000U) +#define MM_DEV_PL_0 (0U) +#define MM_DEV_PL_1 (0U) +#define MM_DEV_PL_2 (0U) +#define MM_DEV_PL_3 (0U) +#define MM_DEV_RTC (0xf12a0000U) +#define MM_DEV_ADMA_0 (0xffa80000U) +#define MM_DEV_ADMA_1 (0xffa90000U) +#define MM_DEV_ADMA_2 (0xffaa0000U) +#define MM_DEV_ADMA_3 (0xffab0000U) +#define MM_DEV_ADMA_4 (0xffac0000U) +#define MM_DEV_ADMA_5 (0xffad0000U) +#define MM_DEV_ADMA_6 (0xffae0000U) +#define MM_DEV_ADMA_7 (0xffaf0000U) +#define MM_DEV_IPI_0 (0xff330000U) +#define MM_DEV_IPI_1 (0xff340000U) +#define MM_DEV_IPI_2 (0xff350000U) +#define MM_DEV_IPI_3 (0xff360000U) +#define MM_DEV_IPI_4 (0xff370000U) +#define MM_DEV_IPI_5 (0xff380000U) +#define MM_DEV_IPI_6 (0xff3a0000U) +#define MM_DEV_DDRMC_0 (0xf6110000U) +#define MM_DEV_DDRMC_1 (0xf6280000U) +#define MM_DEV_DDRMC_2 (0xf63f0000U) +#define MM_DEV_DDRMC_3 (0xf6560000U) +#define MM_DEV_GT_0 (0xf6890000U) +#define MM_DEV_GT_1 (0xf68f0000U) +#define MM_DEV_GT_2 (0xf6940000U) +#define MM_DEV_GT_3 (0xf6990000U) +#define MM_DEV_GT_4 (0xf69e0000U) +#define MM_DEV_GT_5 (0xf6a30000U) +#define MM_DEV_GT_6 (0xf6a90000U) +#define MM_DEV_GT_7 (0xf70e0000U) +#define MM_DEV_GT_8 (0xf7150000U) +#define MM_DEV_GT_9 (0xf71b0000U) +#define MM_DEV_GT_10 (0xf7210000U) +#define MM_DEV_EFUSE_CACHE (0xf1250000U) +#define MM_DEV_AMS_ROOT (0xf1270000U) + +#endif /* __ASM_ARM_PLATFORMS_XILINX_VERSAL_MM_H */