From: Klaus Birkelund Jensen <klaus@birkelund.eu>
Date: Fri, 5 Jul 2019 07:23:18 +0000 (+0200)
Subject: nvme: simplify namespace code
X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=1fa279026d46408872f9426325491350ddd5794a;p=people%2Fpauldu%2Fqemu.git

nvme: simplify namespace code

The device model currently only supports a single namespace and also
specifically sets num_namespaces to 1. Take this into account and
simplify the code.

Signed-off-by: Klaus Birkelund Jensen <klaus.jensen@cnexlabs.com>
---

diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 12d8254250..98b4979306 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -425,7 +425,7 @@ static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
         return NVME_INVALID_NSID | NVME_DNR;
     }
 
-    ns = &n->namespaces[nsid - 1];
+    ns = &n->namespace;
     switch (cmd->opcode) {
     case NVME_CMD_FLUSH:
         return nvme_flush(n, ns, cmd, req);
@@ -671,7 +671,7 @@ static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeIdentify *c)
         return NVME_INVALID_NSID | NVME_DNR;
     }
 
-    ns = &n->namespaces[nsid - 1];
+    ns = &n->namespace;
 
     return nvme_dma_read_prp(n, (uint8_t *)&ns->id_ns, sizeof(ns->id_ns),
         prp1, prp2);
@@ -1307,8 +1307,8 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp)
 {
     NvmeCtrl *n = NVME(pci_dev);
     NvmeIdCtrl *id = &n->id_ctrl;
+    NvmeIdNs *id_ns = &n->namespace.id_ns;
 
-    int i;
     int64_t bs_size;
     uint8_t *pci_conf;
 
@@ -1348,7 +1348,6 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp)
     n->reg_size = pow2ceil(0x1004 + 2 * (n->num_queues + 1) * 4);
     n->ns_size = bs_size / (uint64_t)n->num_namespaces;
 
-    n->namespaces = g_new0(NvmeNamespace, n->num_namespaces);
     n->sq = g_new0(NvmeSQueue *, n->num_queues);
     n->cq = g_new0(NvmeCQueue *, n->num_queues);
 
@@ -1417,20 +1416,10 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp)
 
     }
 
-    for (i = 0; i < n->num_namespaces; i++) {
-        NvmeNamespace *ns = &n->namespaces[i];
-        NvmeIdNs *id_ns = &ns->id_ns;
-        id_ns->nsfeat = 0;
-        id_ns->nlbaf = 0;
-        id_ns->flbas = 0;
-        id_ns->mc = 0;
-        id_ns->dpc = 0;
-        id_ns->dps = 0;
-        id_ns->lbaf[0].ds = BDRV_SECTOR_BITS;
-        id_ns->ncap  = id_ns->nuse = id_ns->nsze =
-            cpu_to_le64(n->ns_size >>
-                id_ns->lbaf[NVME_ID_NS_FLBAS_INDEX(ns->id_ns.flbas)].ds);
-    }
+    id_ns->lbaf[0].ds = BDRV_SECTOR_BITS;
+    id_ns->ncap  = id_ns->nuse = id_ns->nsze =
+        cpu_to_le64(n->ns_size >>
+            id_ns->lbaf[NVME_ID_NS_FLBAS_INDEX(id_ns->flbas)].ds);
 }
 
 static void nvme_exit(PCIDevice *pci_dev)
@@ -1438,7 +1427,6 @@ static void nvme_exit(PCIDevice *pci_dev)
     NvmeCtrl *n = NVME(pci_dev);
 
     nvme_clear_ctrl(n);
-    g_free(n->namespaces);
     g_free(n->cq);
     g_free(n->sq);
 
diff --git a/hw/block/nvme.h b/hw/block/nvme.h
index 557194ee19..40cedb1ec9 100644
--- a/hw/block/nvme.h
+++ b/hw/block/nvme.h
@@ -83,7 +83,7 @@ typedef struct NvmeCtrl {
     uint64_t    timestamp_set_qemu_clock_ms;    /* QEMU clock time */
 
     char            *serial;
-    NvmeNamespace   *namespaces;
+    NvmeNamespace   namespace;
     NvmeSQueue      **sq;
     NvmeCQueue      **cq;
     NvmeSQueue      admin_sq;