From: Michael Clark <mjc@sifive.com>
Date: Sun, 29 Apr 2018 23:06:31 +0000 (+1200)
Subject: RISC-V: Fix missing break statement in disassembler
X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=1dc34be1c90b2d3006078d9d331e53a849cdecf3;p=people%2Fpauldu%2Fqemu.git

RISC-V: Fix missing break statement in disassembler

This fixes an issue when disassembling rv128 c.sqsp,
where the code erroneously fell through to c.swsp.

Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---

diff --git a/disas/riscv.c b/disas/riscv.c
index 2cecf0d855..7fd1019623 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1470,8 +1470,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
             if (isa == rv128) {
                 op = rv_op_c_sqsp;
             } else {
-                op = rv_op_c_fsdsp; break;
+                op = rv_op_c_fsdsp;
             }
+            break;
         case 6: op = rv_op_c_swsp; break;
         case 7:
             if (isa == rv32) {