From: Julien Grall Date: Tue, 27 Feb 2018 11:15:57 +0000 (+0000) Subject: xen/arm: Flush TLBs before turning on the MMU to avoid stale entries X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=1c473c42199a8f4d70533c202e1c57ecd1dad35b;p=people%2Froyger%2Fxen.git xen/arm: Flush TLBs before turning on the MMU to avoid stale entries We don't know what is the state of the TLBs when booting Xen. To avoid stale entries, it is necessary to flush the TLBs before turning on the MMU. Reported-by: Iain Hunter Signed-off-by: Julien Grall Acked-by: Stefano Stabellini --- diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 43374e77c6..612fc8fc3c 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -360,6 +360,13 @@ virtphys_clash: 1: PRINT("- Turning on paging -\r\n") + /* + * The state of the TLBs is unknown before turning on the MMU. + * Flush them to avoid stale one. + */ + mcr CP32(r0, TLBIALLH) /* Flush hypervisor TLBs */ + dsb nsh + ldr r1, =paging /* Explicit vaddr, not RIP-relative */ mrc CP32(r0, HSCTLR) orr r0, r0, #(SCTLR_M|SCTLR_C) /* Enable MMU and D-cache */ diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index fa0ef7034c..90532776bd 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -502,6 +502,13 @@ virtphys_clash: 1: PRINT("- Turning on paging -\r\n") + /* + * The state of the TLBs is unknown before turning on the MMU. + * Flush them to avoid stale one. + */ + tlbi alle2 /* Flush hypervisor TLBs */ + dsb nsh + ldr x1, =paging /* Explicit vaddr, not RIP-relative */ mrs x0, SCTLR_EL2 orr x0, x0, #SCTLR_M /* Enable MMU */