From: Nicholas Piggin <npiggin@gmail.com>
Date: Mon, 13 Nov 2023 12:23:06 +0000 (+1000)
Subject: target/ppc: 440 optimise tlbwe TLB flushing
X-Git-Tag: qemu-xen-4.20.0~284^2~1
X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=1b72973d39b601b3766d157d3d9bf99033c35e7f;p=qemu-xen.git

target/ppc: 440 optimise tlbwe TLB flushing

Have 440 tlbwe flush only the range corresponding to the addresses
covered by the software TLB entry being modified rather than the
entire TLB. This matches what 4xx does.

Tested-by: BALATON Zoltan <balaton@eik.bme.hu>
Acked-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---

diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index 923779d052..ba965f1779 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -864,7 +864,7 @@ void helper_440_tlbwe(CPUPPCState *env, uint32_t word, target_ulong entry,
 
     /* Invalidate previous TLB (if it's valid) */
     if (tlb->prot & PAGE_VALID) {
-        tlb_flush(env_cpu(env));
+        ppcemb_tlb_flush(env_cpu(env), tlb);
     }
 
     switch (word) {