From: Aurelien Jarno Date: Mon, 27 Dec 2010 18:54:49 +0000 (+0100) Subject: target-arm: fix bug in translation of REVSH X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=1a855029af40df40144a322bba0e1e61c68eed2a;p=qemu-xen-4.1-testing.git target-arm: fix bug in translation of REVSH The translation of REVSH shifted the low byte 8 steps left before performing an 8-bit sign extend, causing this part of the expression to alwas be 0. Reported-by: Johan Bengtsson Signed-off-by: Aurelien Jarno --- diff --git a/target-arm/translate.c b/target-arm/translate.c index d4a0666be..24b4fb65e 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -250,13 +250,9 @@ static void gen_rev16(TCGv var) /* Byteswap low halfword and sign extend. */ static void gen_revsh(TCGv var) { - TCGv tmp = new_tmp(); - tcg_gen_shri_i32(tmp, var, 8); - tcg_gen_andi_i32(tmp, tmp, 0x00ff); - tcg_gen_shli_i32(var, var, 8); - tcg_gen_ext8s_i32(var, var); - tcg_gen_or_i32(var, var, tmp); - dead_tmp(tmp); + tcg_gen_ext16u_i32(var, var); + tcg_gen_bswap16_i32(var, var); + tcg_gen_ext16s_i32(var, var); } /* Unsigned bitfield extract. */