From: Edgar E. Iglesias Date: Tue, 4 Oct 2016 12:28:10 +0000 (+0100) Subject: target-arm: A64: Fix decoding of iss_sf in disas_ld_lit X-Git-Tag: qemu-xen-4.9.0-rc1~154^2~1 X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=173ff58580b383a7841b18fddb293038c9d40d1c;p=qemu-xen.git target-arm: A64: Fix decoding of iss_sf in disas_ld_lit Fix the decoding of iss_sf in disas_ld_lit. The SF (Sixty-Four) field in the ISS (Instruction Specific Syndrome) is a bit that specifies the width of the register that the instruction loads to. If cleared it specifies 32 bits. If set it specifies 64 bits. Signed-off-by: Edgar E. Iglesias Message-id: 1475230780-8669-1-git-send-email-edgar.iglesias@gmail.com [PMM: tweaked phrasing per on-list discussion] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index ddf52f5e79..307e281557 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -2025,7 +2025,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn) do_fp_ld(s, rt, tcg_addr, size); } else { /* Only unsigned 32bit loads target 32bit registers. */ - bool iss_sf = opc == 0 ? 32 : 64; + bool iss_sf = opc != 0; do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false, true, rt, iss_sf, false);