From: Edgar E. Iglesias Date: Sun, 26 Mar 2017 21:00:38 +0000 (+0200) Subject: xen/arm64: zynqmp: Regenerate LPD memmap X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=15c7bf27f00bc90afb3e6b7c4a0cf52a7e5ca5b1;p=people%2Fsstabellini%2Fxen-unstable.git%2F.git xen/arm64: zynqmp: Regenerate LPD memmap Regenerate LPD memmap. Signed-off-by: Edgar E. Iglesias --- diff --git a/xen/include/asm-arm/platforms/xilinx-zynqmp-mm.h b/xen/include/asm-arm/platforms/xilinx-zynqmp-mm.h index b1fbd32246..b9b1faecee 100644 --- a/xen/include/asm-arm/platforms/xilinx-zynqmp-mm.h +++ b/xen/include/asm-arm/platforms/xilinx-zynqmp-mm.h @@ -31,52 +31,52 @@ #define MM_ADMA_CH5 0xffad0000 #define MM_ADMA_CH6 0xffae0000 -#define MM_IOU_GPV 0xfe0fffff -#define MM_LPD_GPV 0xfe1fffff -#define MM_USB3_0_XHCI 0xfe2fffff -#define MM_USB3_1_XHCI 0xfe3fffff -#define MM_CORESIGHT_SOC_ROM 0xfe80ffff -#define MM_CORESIGHT_SOC_TSGEN 0xfe90ffff -#define MM_CORESIGHT_SOC_FUNN_0 0xfe91ffff -#define MM_CORESIGHT_SOC_FUNN_1 0xfe92ffff -#define MM_CORESIGHT_SOC_FUNN_2 0xfe93ffff -#define MM_CORESIGHT_SOC_ETF_1 0xfe94ffff -#define MM_CORESIGHT_SOC_ETF_2 0xfe95ffff -#define MM_CORESIGHT_SOC_REPLIC 0xfe96ffff -#define MM_CORESIGHT_SOC_ETR 0xfe97ffff -#define MM_CORESIGHT_SOC_TPIU 0xfe98ffff -#define MM_CORESIGHT_SOC_CTI_0 0xfe99ffff -#define MM_CORESIGHT_SOC_CTI_1 0xfe9affff -#define MM_CORESIGHT_SOC_CTI_2 0xfe9bffff -#define MM_CORESIGHT_SOC_STM 0xfe9cffff -#define MM_CORESIGHT_SOC_FTM 0xfe9dffff -#define MM_CORESIGHT_SOC_ATM_0 0xfe9effff -#define MM_CORESIGHT_SOC_ATM_1 0xfe9fffff -#define MM_CORESIGHT_R5_ROM 0xfebe0fff -#define MM_CORESIGHT_R5_DBG_0 0xfebf0fff -#define MM_CORESIGHT_R5_PMU_0 0xfebf1fff -#define MM_CORESIGHT_R5_DBG_1 0xfebf2fff -#define MM_CORESIGHT_R5_PMU_1 0xfebf3fff -#define MM_CORESIGHT_R5_CTI_0 0xfebf8fff -#define MM_CORESIGHT_R5_CTI_1 0xfebf9fff -#define MM_CORESIGHT_R5_ETM_0 0xfebfcfff -#define MM_CORESIGHT_R5_ETM_1 0xfebfdfff -#define MM_CORESIGHT_A53_ROM 0xfec0ffff -#define MM_CORESIGHT_A53_DBG_0 0xfec1ffff -#define MM_CORESIGHT_A53_CTI_0 0xfec2ffff -#define MM_CORESIGHT_A53_PMU_0 0xfec3ffff -#define MM_CORESIGHT_A53_ETM_0 0xfec4ffff -#define MM_CORESIGHT_A53_DBG_1 0xfed1ffff -#define MM_CORESIGHT_A53_CTI_1 0xfed2ffff -#define MM_CORESIGHT_A53_PMU_1 0xfed3ffff -#define MM_CORESIGHT_A53_ETM_1 0xfed4ffff -#define MM_CORESIGHT_A53_DBG_2 0xfee1ffff -#define MM_CORESIGHT_A53_CTI_2 0xfee2ffff -#define MM_CORESIGHT_A53_PMU_2 0xfee3ffff -#define MM_CORESIGHT_A53_ETM_2 0xfee4ffff -#define MM_CORESIGHT_A53_DBG_3 0xfef1ffff -#define MM_CORESIGHT_A53_CTI_3 0xfef2ffff -#define MM_CORESIGHT_A53_PMU_3 0xfef3ffff +#define MM_IOU_GPV 0xfe000000 +#define MM_LPD_GPV 0xfe100000 +#define MM_USB3_0_XHCI 0xfe200000 +#define MM_USB3_1_XHCI 0xfe300000 +#define MM_CORESIGHT_SOC_ROM 0xfe800000 +#define MM_CORESIGHT_SOC_TSGEN 0xfe900000 +#define MM_CORESIGHT_SOC_FUNN_0 0xfe910000 +#define MM_CORESIGHT_SOC_FUNN_1 0xfe920000 +#define MM_CORESIGHT_SOC_FUNN_2 0xfe930000 +#define MM_CORESIGHT_SOC_ETF_1 0xfe940000 +#define MM_CORESIGHT_SOC_ETF_2 0xfe950000 +#define MM_CORESIGHT_SOC_REPLIC 0xfe960000 +#define MM_CORESIGHT_SOC_ETR 0xfe970000 +#define MM_CORESIGHT_SOC_TPIU 0xfe980000 +#define MM_CORESIGHT_SOC_CTI_0 0xfe990000 +#define MM_CORESIGHT_SOC_CTI_1 0xfe9a0000 +#define MM_CORESIGHT_SOC_CTI_2 0xfe9b0000 +#define MM_CORESIGHT_SOC_STM 0xfe9c0000 +#define MM_CORESIGHT_SOC_FTM 0xfe9d0000 +#define MM_CORESIGHT_SOC_ATM_0 0xfe9e0000 +#define MM_CORESIGHT_SOC_ATM_1 0xfe9f0000 +#define MM_CORESIGHT_R5_ROM 0xfebe0000 +#define MM_CORESIGHT_R5_DBG_0 0xfebf0000 +#define MM_CORESIGHT_R5_PMU_0 0xfebf1000 +#define MM_CORESIGHT_R5_DBG_1 0xfebf2000 +#define MM_CORESIGHT_R5_PMU_1 0xfebf3000 +#define MM_CORESIGHT_R5_CTI_0 0xfebf8000 +#define MM_CORESIGHT_R5_CTI_1 0xfebf9000 +#define MM_CORESIGHT_R5_ETM_0 0xfebfc000 +#define MM_CORESIGHT_R5_ETM_1 0xfebfd000 +#define MM_CORESIGHT_A53_ROM 0xfec00000 +#define MM_CORESIGHT_A53_DBG_0 0xfec10000 +#define MM_CORESIGHT_A53_CTI_0 0xfec20000 +#define MM_CORESIGHT_A53_PMU_0 0xfec30000 +#define MM_CORESIGHT_A53_ETM_0 0xfec40000 +#define MM_CORESIGHT_A53_DBG_1 0xfed10000 +#define MM_CORESIGHT_A53_CTI_1 0xfed20000 +#define MM_CORESIGHT_A53_PMU_1 0xfed30000 +#define MM_CORESIGHT_A53_ETM_1 0xfed40000 +#define MM_CORESIGHT_A53_DBG_2 0xfee10000 +#define MM_CORESIGHT_A53_CTI_2 0xfee20000 +#define MM_CORESIGHT_A53_PMU_2 0xfee30000 +#define MM_CORESIGHT_A53_ETM_2 0xfee40000 +#define MM_CORESIGHT_A53_DBG_3 0xfef10000 +#define MM_CORESIGHT_A53_CTI_3 0xfef20000 +#define MM_CORESIGHT_A53_PMU_3 0xfef30000 #define MM_DDRSS 0xfd000000 #define MM_SATA_AHCI_HBA 0xfd0c0000