From: Andrew Cooper Date: Tue, 9 Apr 2024 14:03:05 +0000 (+0100) Subject: x86/cpuid: Don't expose {IPRED,RRSBA,BHI}_CTRL to PV guests X-Git-Tag: RELEASE-4.15.6~17 X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=13e7c5a9f1b4a6fab563a5994487fc60778073d5;p=xen.git x86/cpuid: Don't expose {IPRED,RRSBA,BHI}_CTRL to PV guests All of these are prediction-mode (i.e. CPL) based. They don't operate as advertised in PV context. Fixes: 4dd676070684 ("x86/spec-ctrl: Expose IPRED_CTRL to guests") Fixes: 478e4787fa64 ("x86/spec-ctrl: Expose RRSBA_CTRL to guests") Fixes: 583f1d095052 ("x86/spec-ctrl: Expose BHI_CTRL to guests") Signed-off-by: Andrew Cooper Acked-by: Roger Pau Monné (cherry picked from commit 4b3da946ad7e3452761478ae683da842e7ff20d6) --- diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index 6e9fbcc38c..0139c1a81f 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -301,9 +301,9 @@ XEN_CPUFEATURE(SRSO_NO, 11*32+29) /*A Hardware not vulenrable to Spe /* Intel-defined CPU features, CPUID level 0x00000007:2.edx, word 13 */ XEN_CPUFEATURE(INTEL_PSFD, 13*32+ 0) /*A MSR_SPEC_CTRL.PSFD */ -XEN_CPUFEATURE(IPRED_CTRL, 13*32+ 1) /*A MSR_SPEC_CTRL.IPRED_DIS_* */ -XEN_CPUFEATURE(RRSBA_CTRL, 13*32+ 2) /*A MSR_SPEC_CTRL.RRSBA_DIS_* */ -XEN_CPUFEATURE(BHI_CTRL, 13*32+ 4) /*A MSR_SPEC_CTRL.BHI_DIS_S */ +XEN_CPUFEATURE(IPRED_CTRL, 13*32+ 1) /*S MSR_SPEC_CTRL.IPRED_DIS_* */ +XEN_CPUFEATURE(RRSBA_CTRL, 13*32+ 2) /*S MSR_SPEC_CTRL.RRSBA_DIS_* */ +XEN_CPUFEATURE(BHI_CTRL, 13*32+ 4) /*S MSR_SPEC_CTRL.BHI_DIS_S */ /* Intel-defined CPU features, CPUID level 0x00000007:1.ecx, word 14 */