From: Philippe Mathieu-Daudé Date: Tue, 21 Jan 2025 11:11:55 +0000 (+0100) Subject: target/arm: Prefer cached CpuClass over CPU_GET_CLASS() macro X-Git-Tag: pull-xen-20250310~3^2~25 X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=0ebdf989c32031019aa0974dbb6b840fca52991e;p=people%2Faperard%2Fqemu-dm.git target/arm: Prefer cached CpuClass over CPU_GET_CLASS() macro CpuState caches its CPUClass since commit 6fbdff87062 ("cpu: cache CPUClass in CPUState for hot code paths"), use it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250122093028.52416-11-philmd@linaro.org> --- diff --git a/target/arm/cpu.c b/target/arm/cpu.c index cacbbc615a..d7e61d08bb 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -830,7 +830,6 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - CPUClass *cc = CPU_GET_CLASS(cs); CPUARMState *env = cpu_env(cs); uint32_t cur_el = arm_current_el(env); bool secure = arm_is_secure(env); @@ -930,7 +929,7 @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) found: cs->exception_index = excp_idx; env->exception.target_el = target_el; - cc->tcg_ops->do_interrupt(cs); + cs->cc->tcg_ops->do_interrupt(cs); return true; } diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 29a41fde69..c4dd309272 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -19,7 +19,6 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - CPUClass *cc = CPU_GET_CLASS(cs); ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; bool ret = false; @@ -35,7 +34,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) if (interrupt_request & CPU_INTERRUPT_HARD && (armv7m_nvic_can_take_pending_exception(env->nvic))) { cs->exception_index = EXCP_IRQ; - cc->tcg_ops->do_interrupt(cs); + cs->cc->tcg_ops->do_interrupt(cs); ret = true; } return ret;