From: Zhao Liu Date: Fri, 10 Jan 2025 14:51:11 +0000 (+0800) Subject: hw/core/machine: Reject thread level cache X-Git-Tag: pull-xen-20250310~34^2~35 X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=0d2d00e57a55d3d8205923e60c2553d83d288ebb;p=people%2Faperard%2Fqemu-dm.git hw/core/machine: Reject thread level cache Currently, neither i386 nor ARM have real hardware support for per- thread cache, and there is no clear demand for this specific cache topology. Additionally, since ARM even can't support this special cache topology in device tree, it is unnecessary to support it at this moment, even though per-thread cache might have potential scheduling benefits for VMs without CPU affinity. Therefore, disable thread-level cache topology in the general machine part. At present, i386 has not enabled SMP cache, so disabling the thread parameter does not pose compatibility issues. In the future, if there is a clear demand for this feature, the correct approach would be to add a new control field in MachineClass.smp_props and enable it only for the machines that require it. Signed-off-by: Zhao Liu Reviewed-by: Michael S. Tsirkin Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20250110145115.1574345-2-zhao1.liu@intel.com> Signed-off-by: Philippe Mathieu-Daudé --- diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c index b954eb8490..4e020c358b 100644 --- a/hw/core/machine-smp.c +++ b/hw/core/machine-smp.c @@ -321,6 +321,13 @@ bool machine_parse_smp_cache(MachineState *ms, return false; } + if (props->topology == CPU_TOPOLOGY_LEVEL_THREAD) { + error_setg(errp, + "%s level cache not supported by this machine", + CpuTopologyLevel_str(props->topology)); + return false; + } + if (!machine_check_topo_support(ms, props->topology, errp)) { return false; }