From: Nicola Vetrini <nicola.vetrini@bugseng.com>
Date: Thu, 29 Jun 2023 10:06:15 +0000 (+0200)
Subject: xen/arm: tlbflush: fix violations of MISRA C:2012 Rule 3.1
X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=0adb4147fdcde50856c02203a1721c5541ef1a32;p=people%2Faperard%2Fxen-unstable.git

xen/arm: tlbflush: fix violations of MISRA C:2012 Rule 3.1

In the files `xen/arch/arm/include/asm/arm(32|64)/flushtlb.h' there are a
few occurrences of nested '//' character sequences inside C-style comment
blocks, which violate Rule 3.1. The patch aims to resolve those by changing
the inner comments to arm asm comments, delimited by ';' instead.

Signed-off-by: Nicola Vetrini <nicola.vetrini@bugseng.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
Reviewed-by: Luca Fancellu <luca.fancellu@arm.com>
---

diff --git a/xen/arch/arm/include/asm/arm32/flushtlb.h b/xen/arch/arm/include/asm/arm32/flushtlb.h
index 22ee3b317b..61c25a3189 100644
--- a/xen/arch/arm/include/asm/arm32/flushtlb.h
+++ b/xen/arch/arm/include/asm/arm32/flushtlb.h
@@ -4,10 +4,10 @@
 /*
  * Every invalidation operation use the following patterns:
  *
- * DSB ISHST        // Ensure prior page-tables updates have completed
- * TLBI...          // Invalidate the TLB
- * DSB ISH          // Ensure the TLB invalidation has completed
- * ISB              // See explanation below
+ * DSB ISHST        ; Ensure prior page-tables updates have completed
+ * TLBI...          ; Invalidate the TLB
+ * DSB ISH          ; Ensure the TLB invalidation has completed
+ * ISB              ; See explanation below
  *
  * For Xen page-tables the ISB will discard any instructions fetched
  * from the old mappings.
diff --git a/xen/arch/arm/include/asm/arm64/flushtlb.h b/xen/arch/arm/include/asm/arm64/flushtlb.h
index 56c6fc763b..45642201d1 100644
--- a/xen/arch/arm/include/asm/arm64/flushtlb.h
+++ b/xen/arch/arm/include/asm/arm64/flushtlb.h
@@ -4,10 +4,10 @@
 /*
  * Every invalidation operation use the following patterns:
  *
- * DSB ISHST        // Ensure prior page-tables updates have completed
- * TLBI...          // Invalidate the TLB
- * DSB ISH          // Ensure the TLB invalidation has completed
- * ISB              // See explanation below
+ * DSB ISHST        ; Ensure prior page-tables updates have completed
+ * TLBI...          ; Invalidate the TLB
+ * DSB ISH          ; Ensure the TLB invalidation has completed
+ * ISB              ; See explanation below
  *
  * ARM64_WORKAROUND_REPEAT_TLBI:
  * Modification of the translation table for a virtual address might lead to